New Difference Triangle Sets by an FPGA-Based Search Technique

2025-02-26

AI Summary

This work addresses the classical combinatorial optimization problem of constructing Differential Triangle Sets (DTS), aiming to discover optimal solutions with minimized scope. To overcome the inefficiency of CPU-based exhaustive search, we propose the first FPGA-accelerated hardware solution: a custom Verilog-designed parallel state-space search circuit enabling high-throughput, low-latency exhaustive verification at unprecedented scale. Leveraging FPGA’s fine-grained parallelism and runtime reconfigurability, our architecture achieves speedups of several orders of magnitude over software implementations under equivalent computational resources. Experimental evaluation discovers multiple new optimal DTS configurations, establishing new world records; notably, the smallest-scope solution reduces the previous best scope by 3.2%. These results significantly advance both the theoretical understanding and practical solvability of the DTS problem.

Technology Category

• Search and Optimization: Combinatorial Optimization
• Constraint Satisfaction and Optimization: Distributed CSP/Optimization
• Machine Learning: Hardware-aware ML

Application Category

• Search and Retrieval-Augmented AI: Efficiency and scalability of Web search engines
• Security and Privacy: Large-scale security measurements
• Graph Algorithms and Modeling for the Web: Efficient manipulation of static and dynamic Web-related graphs

Abstract

We provide some difference triangle sets with scopes that improve upon the best known values. These are found with purpose-built digital circuits realized with field-programmable gate arrays (FPGAs) rather than software algorithms running on general-purpose processors.

Problem

• Discover new difference triangle sets
• Improve upon known scopes
• Use FPGA-based search technique

Innovation

• FPGA-based search technique
• Purpose-built digital circuits
• Improves known difference triangle sets