SAF: Scalable Acceleration Framework for dynamic and flexible scaling of FPGAs

2025-03-02

AI Summary

Traditional FPGA systems are constrained by PCIe-based architectures, limiting scalable deployment due to inflexible expansion, lack of multi-device synchronized reconfiguration, and dependency on host computers. This paper proposes an Ethernet-based scalable FPGA acceleration framework, introducing the first host-independent FPGA-to-Ethernet direct-connect architecture. It integrates a customized shell and a lightweight protocol stack to enable hot-plug capability and concurrent dynamic reconfiguration across multiple FPGAs. Implemented on Intel Arria-10 FPGAs using the Bittware 385A platform, the system leverages OpenCL SDK and a custom Ethernet protocol stack. Experimental results demonstrate a 13× improvement in reconfiguration speed, 38% reduction in hardware cost, 25% decrease in application execution time, and 27% lower energy consumption. Furthermore, the framework achieves near-linear weak and strong scalability on the PTRANS benchmark.

Technology Category

• Machine Learning: Hardware-aware ML
• Data Mining & Knowledge Management: Scalability, Parallel & Distributed Systems
• Cognitive Modeling & Cognitive Systems: Agent Architectures

Application Category

• Systems and Infrastructure for Web, Mobile and WoT: Experiences and lessons learnt from Web-based algorithms and system deployments
• Search and Retrieval-Augmented AI: Efficiency and scalability of Web search engines
• Economics, Online Markets and Human Computation: Incentives in network design for Web infrastructures and ecosystems

Abstract

FPGAs are increasingly gaining traction in cloud and edge computing environments due to their hardware flexibility, low latency, and low energy consumption. However, the existing hardware stack of FPGA and the host-FPGA connectivity does not allow flexible scaling and simultaneous reconfiguration of multiple devices, which limits the adoption of FPGA at scale. In this paper, we present SAF -- an Ethernet-based scalable acceleration framework that allows FPGA to be hot-plugged into a network in a stand-alone fashion without connecting to a local host CPU, which enables flexible scalability. SAF provides a custom FPGA shell and a set of Ethernet protocols that allow FPGAs to connect with a remote host to accelerate application kernels. SAF can configure multiple FPGAs simultaneously, which significantly reduces the reconfiguration time in scaling effort. We implemented the SAF framework using Intel FPGA SDK for OpenCL and 20 Bittware 385A cards with Arria-10 FPGAs. We analyze a case study and conduct experiments to compare SAF with state-of-the-art multi-FPGA clusters. Results show that SAF provides 13X faster reconfiguration than sequential PCIe programming, reduces the hardware setup costs by 38%, application runtime by 25%, and energy consumption by 27%. We evaluated the performance scalability of SAF using the PTRANS benchmark of the HPCC FPGA benchmark suite and showed an almost linear speedup for strong and weak scaling scenarios.

Problem

• Enables flexible scaling of FPGAs in cloud and edge computing.
• Reduces reconfiguration time for multiple FPGAs simultaneously.
• Improves hardware setup costs, application runtime, and energy efficiency.

Innovation

• Ethernet-based framework for FPGA scalability
• Simultaneous reconfiguration of multiple FPGAs
• Custom FPGA shell with remote host connectivity