🤖 AI Summary
RISC-V processors lack dedicated microarchitectural side-channel—particularly cache-timing—security assessment tools. Method: This work systematically ports the mainstream x86-64 cache-timing vulnerability benchmark suite to the RISC-V ecosystem, establishing the first cross-ISA side-channel evaluation framework. Using this framework, we conduct empirical analyses on commercial RISC-V cores, including the T-Head C910 and SiFive U54/U74. Contribution/Results: We find that 37.5% of vulnerabilities are pervasive across all tested cores, while only 6.8% remain undetected; the C910 exhibits more complex cache-timing behavior, indicating elevated security risk. This study fills a critical gap in quantitative microarchitectural security assessment for RISC-V, providing a reusable methodology and empirical foundation for early vulnerability identification and security-aware processor design.
📝 Abstract
While interest in the open RISC-V instruction set architecture is growing, tools to assess the security of concrete processor implementations are lacking. There are dedicated tools and benchmarks for common microarchitectural side-channel vulnerabilities for popular processor families such as Intel x86-64 or ARM, but not for RISC-V. In this paper we describe our efforts in porting an Intel x86-64 benchmark suite for cache-based timing vulnerabilities to RISC-V. We then use this benchmark to evaluate the security of three commercially available RISC-V processors, the T-Head C910 and the SiFive U54 and U74 cores. We observe that the C910 processor exhibits more distinct timing types than the other processors, leading to the assumption that code running on the C910 would be exposed to more microarchitectural vulnerability sources. In addition, our evaluation reveals that $37.5%$ of the vulnerabilities covered by the benchmark exist in all processors, while only $6.8%$ are absent from all cores. Our work, in particular the ported benchmark, aims to support RISC-V processor designers to identify leakage sources early in their designs and to support the development of countermeasures.