Sequencing on Silicon: AI SoC Design for Mobile Genomics at the Edge

2025-10-10

AI Summary

To address the challenge of real-time analysis of nanopore sequencing data—whose sampling rate exceeds audio bandwidth by over two orders of magnitude and thus overwhelms mobile edge devices—this paper proposes a heterogeneous SoC architecture tailored for mobile genomics. Built in CMOS technology, it integrates a multi-core RISC-V processor with domain-specific accelerators for deep learning and bioinformatics, and jointly optimizes temporal-signal neural networks, memory access patterns, and the full software-hardware stack. To our knowledge, this is the first design enabling end-to-edge, full-stack real-time analysis—from raw nanopore electrical signals to variant calling—while maintaining sub-1-W power consumption and achieving >500 Mbps throughput. Experimental evaluation demonstrates an 8.3× improvement in energy efficiency over a state-of-the-art ARM-based general-purpose platform, substantially reducing reliance on cloud or HPC resources. The architecture establishes a scalable hardware foundation for portable, real-time genomic diagnostics.

Technology Category

• Machine Learning: Hardware-aware ML
• Search and Optimization: Evolutionary Computation
• Cognitive Modeling & Cognitive Systems: Neural Spike Coding

Application Category

• Systems and Infrastructure for Web, Mobile and WoT: Energy management for devices in mobile Web and WoT environments
• Security and Privacy: Data transparency and provenance
• Economics, Online Markets and Human Computation: Economic ramifications for generative AI infrastructure and applications

Abstract

Miniature DNA sequencing hardware has begun to succeed in mobile contexts, driving demand for efficient machine learning at the edge. This domain leverages deep learning techniques familiar from speech and time-series analysis for both low-level signal processing and high-level genomic interpretation. Unlike audio, however, nanopore sequencing presents raw data rates over 100X higher, requiring more aggressive compute and memory handling. In this paper, we present a CMOS system-on-chip (SoC) designed for mobile genetic analysis. Our approach combines a multi-core RISC-V processor with tightly coupled accelerators for deep learning and bioinformatics. A hardware/software co-design strategy enables energy-efficient operation across a heterogeneous compute fabric, targeting real-time, on-device genome analysis. This work exemplifies the integration of deep learning, edge computing, and domain-specific hardware to advance next-generation mobile genomics.

Problem

• Designing AI SoC for mobile genomics at the edge
• Handling nanopore sequencing's high raw data rates
• Enabling real-time on-device genome analysis efficiently

Innovation

• AI SoC with RISC-V processor and accelerators
• Hardware-software co-design for energy efficiency
• Deep learning integration for mobile genomics