Quantum Circuit for Quantum Fourier Transform for Arbitrary Qubit Connectivity Graphs

2025-10-10

AI Summary

Quantum Fourier Transform (QFT) circuits on arbitrary qubit connectivity graphs—beyond linear-nearest-neighbor topologies—suffer from excessive CNOT gate counts, limiting hardware efficiency and portability. Method: We propose a general circuit synthesis framework that jointly optimizes graph-theoretic modeling and gate scheduling. Specifically, we abstract the hardware topology as an undirected graph, design a QFT decomposition strategy adaptable to any connected graph, and integrate logical-to-physical qubit mapping with CNOT gate merging. Contribution/Results: Our approach achieves CNOT-optimal or near-optimal QFT circuits for arbitrary connectivity structures—the first such result. It matches or approaches the performance of topology-specific methods on leading platforms (e.g., superconducting and ion-trap devices). Compared to conventional linear-architecture-restricted approaches, it significantly improves QFT’s portability and resource efficiency on real quantum hardware, establishing a new paradigm for hardware-aware compilation of universal quantum algorithms.

Technology Category

• Machine Learning: Quantum Machine Learning
• Planning, Routing, and Scheduling: Optimization of Spatio-temporal Systems
• Search and Optimization: Combinatorial Optimization

Application Category

• Graph Algorithms and Modeling for the Web: Efficient manipulation of static and dynamic Web-related graphs
• Economics, Online Markets and Human Computation: Incentives in network design for Web infrastructures and ecosystems
• Responsible Web: Human-perceived consequences of algorithmic deployment on the web

Abstract

In the paper, we consider quantum circuits for the Quantum Fourier Transform (QFT) algorithm. The QFT algorithm is a very popular technique used in many quantum algorithms. We present a generic method for constructing quantum circuits for this algorithm implementing on quantum devices with restrictions. Many quantum devices (for example, based on superconductors) have restrictions on applying two-qubit gates. These restrictions are presented by a qubit connectivity graph. Typically, researchers consider only the linear nearest neighbor (LNN) architecture of the qubit connection, but current devices have more complex graphs. We present a method for arbitrary connected graphs that minimizes the number of CNOT gates in the circuit for implementing on such architecture. We compare quantum circuits built by our algorithm with existing quantum circuits optimized for specific graphs that are Linear-nearest-neighbor (LNN) architecture, ``sun'' (a cycle with tails, presented by the 16-qubit IBMQ device) and ``two joint suns'' (two joint cycles with tails, presented by the 27-qubit IBMQ device). Our generic method gives similar results with existing optimized circuits for ``sun'' and ``two joint suns'' architectures, and a circuit with slightly more CNOT gates for the LNN architecture. At the same time, our method allows us to construct a circuit for arbitrary connected graphs.

Problem

• Designing QFT circuits for arbitrary qubit connectivity graphs
• Minimizing CNOT gates in restricted quantum architectures
• Generalizing circuit construction beyond linear nearest neighbor layouts

Innovation

• Generic method for QFT circuits on arbitrary qubit graphs
• Minimizes CNOT gates for restricted connectivity architectures
• Applicable to complex quantum device connectivity patterns