ShuffleV: A Microarchitectural Defense Strategy against Electromagnetic Side-Channel Attacks in Microprocessors

2025-10-14

AI Summary

Electromagnetic (EM) emanations from microprocessors during runtime pose a severe side-channel threat, enabling leakage of sensitive information such as cryptographic keys and neural network hyperparameters. To mitigate this, we propose ShuffleV—a hardware-level microarchitectural defense grounded in Moving Target Defense (MTD) principles. ShuffleV integrates an instruction randomization unit and a virtual instruction insertion module into a RISC-V processor core, dynamically perturbing execution timing and EM signatures to fundamentally degrade cross-trace statistical analysis. The design requires no software modifications or user intervention and supports configurable security strength. Evaluated on a Xilinx PYNQ-Z2 FPGA prototype, ShuffleV demonstrates robust protection against EM side-channel attacks on AES encryption and neural network inference, with average performance overhead below 4.2%. This represents a significant improvement over state-of-the-art countermeasures in both efficacy and efficiency.

Technology Category

• Machine Learning: Hardware-aware ML
• Computer Vision: Adversarial Attacks & Robustness
• Multiagent Systems: Adversarial Agents

Application Category

• Security and Privacy: Privacy-enhancing technologies
• User Modeling, Personalization and Recommendation: Attacks and countermeasures in recommendation systems
• Responsible Web: Data and user privacy-enhancing technologies for the Web

Abstract

The run-time electromagnetic (EM) emanation of microprocessors presents a side-channel that leaks the confidentiality of the applications running on them. Many recent works have demonstrated successful attacks leveraging such side-channels to extract the confidentiality of diverse applications, such as the key of cryptographic algorithms and the hyperparameter of neural network models. This paper proposes ShuffleV, a microarchitecture defense strategy against EM Side-Channel Attacks (SCAs). ShuffleV adopts the moving target defense (MTD) philosophy, by integrating hardware units to randomly shuffle the execution order of program instructions and optionally insert dummy instructions, to nullify the statistical observation by attackers across repetitive runs. We build ShuffleV on the open-source RISC-V core and provide six design options, to suit different application scenarios. To enable rapid evaluation, we develop a ShuffleV simulator that can help users to (1) simulate the performance overhead for each design option and (2) generate an execution trace to validate the randomness of execution on their workload. We implement ShuffleV on a Xilinx PYNQ-Z2 FPGA and validate its performance with two representative victim applications against EM SCAs, AES encryption, and neural network inference. The experimental results demonstrate that ShuffleV can provide automatic protection for these applications, without any user intervention or software modification.

Problem

• Defends microprocessors against electromagnetic side-channel attacks
• Randomizes instruction execution order to nullify statistical analysis
• Protects cryptographic algorithms and neural networks without software changes

Innovation

• Randomly shuffles instruction execution order
• Inserts dummy instructions to confuse attackers
• Uses moving target defense philosophy