ColumnDisturb: Understanding Column-based Read Disturbance in Real DRAM Chips and Implications for Future Systems

2025-10-16

AI Summary

This work identifies and systematically characterizes ColumnDisturb—a novel column-level read disturbance phenomenon in DRAM—where sustained activation of a single row induces multi-bit failures across up to 3,072 rows via shared bitlines across sub-arrays, exceeding RowHammer’s spatial impact. Through empirical evaluation on 216 DDR4 and 4 HBM2 commercial chips (spanning three major vendors, multiple technology nodes, and operating conditions), we demonstrate that ColumnDisturb triggers bit flips within standard refresh intervals; in worst cases, the number of affected rows reaches 198× that of conventional retention failures, worsening significantly with technology scaling. Crucially, ColumnDisturb fundamentally undermines existing retention-aware refresh mechanisms, as it manifests independently of cell leakage and cannot be mitigated by conventional timing-based refresh policies. These findings establish a critical foundation for next-generation DRAM reliability modeling and refresh strategy design.

Technology Category

• Search and Optimization: Distributed Search
• Machine Learning: Hardware-aware ML
• Data Mining & Knowledge Management: Scalability, Parallel & Distributed Systems

Application Category

• Search and Retrieval-Augmented AI: Vertical and domain-specific search
• Security and Privacy: Large-scale security measurements
• Responsible Web: Data and user privacy-enhancing technologies for the Web

Abstract

We experimentally demonstrate a new widespread read disturbance phenomenon, ColumnDisturb, in real commodity DRAM chips. By repeatedly opening or keeping a DRAM row (aggressor row) open, we show that it is possible to disturb DRAM cells through a DRAM column (i.e., bitline) and induce bitflips in DRAM cells sharing the same columns as the aggressor row (across multiple DRAM subarrays). With ColumnDisturb, the activation of a single row concurrently disturbs cells across as many as three subarrays (e.g., 3072 rows) as opposed to RowHammer/RowPress, which affect only a few neighboring rows of the aggressor row in a single subarray. We rigorously characterize ColumnDisturb and its characteristics under various operational conditions using 216 DDR4 and 4 HBM2 chips from three major manufacturers. Among our 27 key experimental observations, we highlight two major results and their implications. First, ColumnDisturb affects chips from all three major manufacturers and worsens as DRAM technology scales down to smaller node sizes (e.g., the minimum time to induce the first ColumnDisturb bitflip reduces by up to 5.06x). We observe that, in existing DRAM chips, ColumnDisturb induces bitflips within a standard DDR4 refresh window (e.g., in 63.6 ms) in multiple cells. We predict that, as DRAM technology node size reduces, ColumnDisturb would worsen in future DRAM chips, likely causing many more bitflips in the standard refresh window. Second, ColumnDisturb induces bitflips in many (up to 198x) more rows than retention failures. Therefore, ColumnDisturb has strong implications for retention-aware refresh mechanisms that leverage the heterogeneity in cell retention times: our detailed analyses show that ColumnDisturb greatly reduces the benefits of such mechanisms.

Problem

• Characterizing a new widespread read disturbance phenomenon in DRAM chips
• Analyzing how repeated row activation induces bitflips across multiple subarrays
• Investigating implications for future DRAM scaling and refresh mechanisms

Innovation

• ColumnDisturb exploits column-based read disturbance in DRAM
• Activating a single row disturbs cells across multiple subarrays
• Characterized using 216 DDR4 and 4 HBM2 chips