🤖 AI Summary
This work addresses the challenge that RTL code generated in a single pass by large language models (LLMs) often fails to simultaneously achieve functional correctness and power efficiency. To overcome this limitation, the authors propose a novel control framework based on simulated annealing, introducing this optimization mechanism for the first time into LLM-driven hardware design. The approach first filters functionally correct candidate designs through compilation, structural checking, and simulation, and then performs power-performance-area (PPA) co-optimization over this validated subset. By decoupling functional verification from PPA refinement into distinct yet coordinated stages, the method significantly improves both functional correctness rates and the stability and reproducibility of PPA outcomes across eight RTL benchmark designs.
📝 Abstract
Large Language Models (LLMs) have shown promising progress for generating Register Transfer Level (RTL) hardware designs, largely because they can rapidly propose alternative architectural realizations. However, single-shot LLM generation struggles to consistently produce designs that are both functionally correct and power-efficient. This paper proposes HYPERHEURIST, a simulated annealing-based control framework that treats LLM-generated RTL as intermediate candidates rather than final designs. The suggested system not only focuses on functionality correctness but also on Power-Performance-Area (PPA) optimization. In the first phase, RTL candidates are filtered through compilation, structural checks, and simulation to identify functionally valid designs. PPA optimization is restricted to RTL designs that have already passed compilation and simulation. Evaluated across eight RTL benchmarks, this staged approach yields more stable and repeatable optimization behavior than single-pass LLM-generated RTL.