Scholar
Jitendra Bhandari
Google Scholar ID: -wQyn7cAAAAJ
PhD Student, New York University
Hardware Security
Side Channel Analysis
LLM for Hardware
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Citations & Impact
All-time
Citations
236
H-index
9
i10-index
9
Publications
20
Co-authors
0
Publications
7 items
VeriLoC: Line-of-Code Level Prediction of Hardware Design Quality from Verilog Code
2025
Cited
0
SALAD: Systematic Assessment of Machine Unlearing on LLM-Aided Hardware Design
2025
Cited
0
ARIANNA: An Automatic Design Flow for Fabric Customization and eFPGA Redaction
2025
Cited
0
VeriContaminated: Assessing LLM-Driven Verilog Coding for Data Contamination
2025
Cited
0
VeriLeaky: Navigating IP Protection vs Utility in Fine-Tuning for LLM-Driven Verilog Coding
2025
Cited
0
Masala-CHAI: A Large-Scale SPICE Netlist Dataset for Analog Circuits by Harnessing AI
arXiv.org · 2024
Cited
0
LLM-Aided Testbench Generation and Bug Detection for Finite-State Machines
arXiv.org · 2024
Cited
10
