Scholar
Luca Bertaccini
Google Scholar ID: 0oCATVYAAAAJ
ETH Zurich
Digital ASIC Design
Hardware Accelerators
Heterogenous SoCs
Embedded Systems
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Citations & Impact
All-time
Citations
190
H-index
9
i10-index
9
Publications
20
Co-authors
15
list available
Contact
No contact links provided.
Publications
5 items
MXDOTP: A RISC-V ISA Extension for Enabling Microscaling (MX) Floating-Point Dot Products
2025
Cited
0
RedMulE-FT: A Reconfigurable Fault-Tolerant Matrix Multiplication Engine
2025
Cited
0
Maestro: A 302 GFLOPS/W and 19.8GFLOPS RISC-V Vector-Tensor Architecture for Wearable Ultrasound Edge Computing
2025
Cited
0
A Reliable, Time-Predictable Heterogeneous SoC for AI-Enhanced Mixed-Criticality Edge Applications
2025
Cited
0
Occamy: A 432-Core Dual-Chiplet Dual-HBM2E 768-DP-GFLOP/s RISC-V System for 8-to-64-bit Dense and Sparse Computing in 12nm FinFET
2025
Cited
0
Resume (English only)
Co-authors
15 total
Luca Benini
ETH Zürich, Università di Bologna
Davide Rossi
Associate Professor, University Of Bologna
Francesco Conti
Associate Professor, University of Bologna
Co-author 4
Tim Fischer
PhD Student, ETH Zurich
Matheus Cavalcante
Stanford University
Yvan Tortorella
University of Bologna
Frank K. Gürkaynak
Senior Scientist, ETH Zurich
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