Abhilasha Dave
Scholar

Abhilasha Dave

Google Scholar ID: 1eKN4-UAAAAJ
Stanford
Machine Learning Hardware AcceleratorsMachine LearningHigh Performance Computer Architecture
Homepage↗Google Scholar↗
Citations & Impact
All-time
Citations
10
 
H-index
2
 
i10-index
0
 
Publications
6
 
Co-authors
0
 
Publications
6 items
A packet-level digital hardware twin for commissioning megahertz diagnostic edge AI and plasma control system integration in tokamaks
2026
Cited
0
Classical Hardware Acceleration of Quantum Autoencoders for Real-Time Anomaly Detection in Collider Experiments
2026
Cited
0
HeteroViT: A Versatile Single-Layer Vision Transformer Concept, Co-Designed for Distributed Real-Time Data Reduction on Scientific Detectors
2026
Cited
0
Hardware-Aware Tensor Networks for Real-Time Quantum-Inspired Anomaly Detection at Particle Colliders
2026
Cited
0
Neural Network Acceleration on MPSoC board: Integrating SLAC's SNL, Rogue Software and Auto-SNL
2025
Cited
0
FPGA-Accelerated SpeckleNN with SNL for Real-time X-ray Single-Particle Imaging
2025
Cited
0
Resume
Academic Achievements
  • Published multiple papers in venues such as IEEE Journal on Emerging and Selected Topics in Circuits and Systems
  • Published 'Hw/sw codesign for approximation-aware binary neural networks' in 2023
  • Posted arXiv preprint 'Analysis of Hardware Synthesis Strategies for Machine Learning in Collider Trigger and Data Acquisition' in 2024
  • Published 2025 works on FPGA-accelerated SpeckleNN and neural network acceleration on MPSoC boards
  • Google Scholar h-index of 2 with 10 total citations (as of 2025)