Hira Taqdees Syeda
Scholar

Hira Taqdees Syeda

Google Scholar ID: 4PWt3HEAAAAJ
Lecturer at University of Melbourne
Formal MethodsInteractive Theorem ProvingSoftware VerificationEmbedded Systems Design and
Citations & Impact
All-time
Citations
101
 
H-index
6
 
i10-index
5
 
Publications
15
 
Co-authors
12
list available
Resume (English only)
Academic Achievements
  • Journal paper: 'Formal reasoning under cached address translation' (JAR 2020, with Gerwin Klein).
  • Journal paper: 'Formally verifying transfer functions of linear analog circuits' (IEEE Design & Test 2017, with Osman Hasan).
  • Conference paper: 'Do you have space for dessert? a verified space cost semantics for CakeML programs' (OOPSLA 2020).
  • Conference paper: 'Program verification in the presence of cached address translation' (ITP 2018, with Gerwin Klein).
  • Conference paper: 'Reasoning about translation lookaside buffers' (LPAR 2017, with Gerwin Klein).
  • Conference paper: 'Formalization of Laplace transform using the multivariable calculus theory of HOL Light' (LPAR 2013, with Osman Hasan).
  • Served on program or artifact evaluation committees and as reviewer for major conferences including CPP 2022 (PC member), CAV 2021 (Artifact Evaluation), and ITP, FM, ICFP, CADE, etc.