Scholar
Xiangchen Meng
Google Scholar ID: 8eT7CZsAAAAJ
The Hong Kong University of Science and Technology (Guangzhou)
RTL Verification
Fully Homomorphic Encryption
Hardware Accelerator
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Citations & Impact
All-time
Citations
7
H-index
2
i10-index
0
Publications
6
Co-authors
3
list available
Publications
5 items
ChipVerilog: A Large-Scale OpenCores-Derived Benchmark for LLM-Based Verilog RTL Generation
2026
Cited
0
VerilogCL: A Contrastive Learning Framework for Robust LLM-Based Verilog Generation
2026
Cited
0
AutoVeriFix+: High-Correctness RTL Generation via Trace-Aware Causal Fix and Semantic Redundancy Pruning
2026
Cited
0
FedBit: Accelerating Privacy-Preserving Federated Learning via Bit-Interleaved Packing and Cross-Layer Co-Design
2025
Cited
0
AutoVeriFix: Automatically Correcting Errors and Enhancing Functional Correctness in LLM-Generated Verilog Code
2025
Cited
0
Co-authors
2 total
Yangdi Lyu
The Hong Kong University of Science and Technology (Guangzhou)
Zijun Jiang
HKUST(GZ)
