Scholar
Robert Szafarczyk
Google Scholar ID: LBaBZiMAAAAJ
Ph.D. student, University of Glasgow
Citations & Impact
Citations
22
H-index
2
i10-index
1
Publications
7
Co-authors
0
Publications
Resume (English only)
Academic Achievements
- - Compiler-Hardware Co-Design in High-Level Synthesis, PhD Thesis, University of Glasgow, 2025
- - Compiler Support for Speculation in Decoupled Access/Execute Architectures, In the Proceedings of the 34th ACM SIGPLAN International Conference on Compiler Construction (CC), Las Vegas, USA, 2025
- - Dynamic Loop Fusion in High-Level Synthesis, In the Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays (FPGA), Monterey, CA, USA, 2025
- - A High-Frequency Load-Store Queue with Speculative Allocations for High-Level Synthesis, In the International Conference on Field Programmable Technology (ICFPT), Yokohama, Japan, 2023
- - Compiler Discovered Dynamic Scheduling of Irregular Code in High-Level Synthesis, In the 33rd International Conference on Field-Programmable Logic and Applications (FPL), Gothenburg, Sweden, 2023 (Michal Servit Best Paper Award)
- - Dynamically Scheduled Memory Operations in Static High-Level Synthesis, In the 31st International Symposium On Field-Programmable Custom Computing Machines (FCCM), Los Angeles, US, 2023 (extended abstract)
- - Reducing FPGA Memory Footprint of Stencil Codes through Automatic Extraction of Memory Patterns, In the 32nd International Conference on Field Programmable Logic and Applications (FPL), Belfast, UK, 2022 (short paper)
- - Accelerating Biological Sequence Alignment Using a GPU, BSc thesis, University of Liverpool, 2021
Research Experience
- - Senior Engineer, Qualcomm, 2025 - present
- - Wireless Software Engineer (Year in Industry Intern), Intel, 2019 – 2020
Education
- - PhD in Computer Science, University of Glasgow, 2021 – 2025
- - BSc in Computer Science with a Year in Industry, University of Liverpool, 2021, First Class Degree with Honours
Background
- A senior engineer at Qualcomm working on GPU compilers. Previously, a PhD student at the University of Glasgow focusing on compilers and programming models for spatial dataflow architectures. His PhD thesis was about instruction scheduling in High-Level Synthesis, covering modulo scheduling, out-of-order execution, speculative execution, and decoupled access/execute; with a focus on the interaction between the compiler and hardware. He also dabbled in programming language theory topics related to hardware design, particularly Bluespec-like models of execution based on rewrite rules.
Miscellany
- Past academic duties include being an Artefact Evaluation committee member for the 28th International European Conference on Parallel and Distributed Computing (EURO-PAR '22), a reviewer for the Journal of Open Source Software (JOSS), and tutoring multiple courses at the University of Glasgow and the University of Liverpool.
Co-authors