Cheng Liu (刘成)
Scholar

Cheng Liu (刘成)

Google Scholar ID: LVWU_VQAAAAJ
Institute of Computing Technology, Chinese Academy of Sciences
Domain-Specific Architecture and SystemLLM4ChipFault-Tolerant Computing
Citations & Impact
All-time
Citations
1,555
 
H-index
22
 
i10-index
44
 
Publications
20
 
Co-authors
8
list available
Publications
20 items
Browse publications on Google Scholar (top-right) ↗
Resume (English only)
Academic Achievements
  • Published multiple papers and received awards, such as the work on DRAM-PIM based ANNS Engine accepted by SC’25, DSL for FPGA-based graph processing accelerator generation accepted by LCTES’25, and FrontOrder approach accepted by ICDE’25. Also, won the Huawei OlympusMons Award in 2024, and placed second in DAC'23 SDC and third in DAC'22 SDC.
Research Experience
  • Worked as a research fellow at National University of Singapore from 2016 to 2018, and then joined ICT as an associate professor.
Education
  • Received B.Eng and M.Eng degrees from Harbin Institute of Technology, and a Ph.D. degree from The University of Hong Kong in 2016, advised by Prof. Hayden So.
Background
  • Research interests include computer architecture, integrated circuits, and EDA. Currently an associate professor at the State Key Laboratory of Processors (SKLP), Institute of Computing Technology (ICT), Chinese Academy of Sciences (CAS).
Miscellany
  • Looking for self-motivated master/intern students for LLM-based intelligent chip designs, including tasks like RISC-V SoC design and verification, RISC-V ASIP design automation, etc. Remote work is possible.