Scholar
Joshua Kalyanapu
Google Scholar ID: OifmorUAAAAJ
Ph.D Candidate, North Carolina State University
microarchitectural side-channel attacks
formal verification
microarchitecture
accelerator
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Citations & Impact
All-time
Citations
10
H-index
2
i10-index
0
Publications
6
Co-authors
0
Publications
5 items
TranScope: What the Software Hides About LLM Training Data, the Hardware Reveals at Scale, and Accelerators Magnify
2026
Cited
0
CacheFit: The Rising Cost of Cache Replacement and Constraint-Driven Redesign of Last-Level Cache Replacement Policies
2026
Cited
0
FeatureBleed: Inferring Private Enriched Attributes From Sparsity-Optimized AI Accelerators
2026
Cited
0
GATEBLEED: Exploiting On-Core Accelerator Power Gating for High Performance & Stealthy Attacks on AI
2025
Cited
0
THOR: A Non-Speculative Value Dependent Timing Side Channel Attack Exploiting Intel AMX
2025
Cited
0
