Scholar
Jinming Lu
Google Scholar ID: Q3xguTwAAAAJ
University of California, Santa Barbara
Deep Learning
VLSI
Hardware Aceeleration
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Citations & Impact
All-time
Citations
311
H-index
8
i10-index
8
Publications
20
Co-authors
7
list available
Publications
7 items
ZOAF: Towards Efficient Zeroth-Order Optimization for Analog/RF Circuit Design
2026
Cited
0
Tensor-Compressed and Fully-Quantized Training of Neural PDE Solvers
2025
Cited
0
Comprehensive Design Space Exploration for Tensorized Neural Network Hardware Accelerators
2025
Cited
0
FLAT-LLM: Fine-grained Low-rank Activation Space Transformation for Large Language Model Compression
2025
Cited
0
FETTA: Flexible and Efficient Hardware Accelerator for Tensorized Neural Network Training
2025
Cited
0
CDM-QTA: Quantized Training Acceleration for Efficient LoRA Fine-Tuning of Diffusion Model
2025
Cited
0
Ultra Memory-Efficient On-FPGA Training of Transformers via Tensor-Compressed Optimization
2025
Cited
0
Co-authors
6 total
Zhongfeng Wang
Nanjing University
Chao Fang
Shanghai Qi Zhi Institute
Zhisheng Wang
Huawei Hisilicon
Siyuan Lu
Nanjing University
Wendong Mao
Sun Yat-Sen University, Assistant Professor
Zheng Zhang
Professor of ECE, UCSB
