Zhe Jiang
Scholar

Zhe Jiang

Google Scholar ID: V5e-7hcAAAAJ
Southeast University, People's Republic of China.
(Micro-)ArchitectureEmbedded SystemDesign AutomationSafetyReal-time
Citations & Impact
All-time
Citations
652
 
H-index
15
 
i10-index
26
 
Publications
20
 
Co-authors
22
list available
Resume (English only)
Academic Achievements
  • Details about publications, awards, patents, etc., are not provided.
Research Experience
  • Postdoctoral scholar (2021-2024), Computer Architecture Group, Department of Computer Science and Technology, University of Cambridge, UK, worked with Timothy M. Jones and Sam Ainsworth to explore microarchitectural supports to improve the security and reliability of out-of-order superscalar processors; Design engineer (2020-2022), Central Engineering, ARM, UK, worked on the architecture and micro-architecture for server System-on-Chips (SoCs); Safety architect (2018-2020), Functional Safety Competency Centre (FSCC), Renesas Electronics, UK, worked on the architecture and safety architecture for automotive micro-controllers.
Education
  • PhD (2014 - 2018), Real-Time Systems Group, Department of Computer Science, University of York, UK, supervised by Neil Audsley; research focused on the architecture and micro-architecture for real-time Network-on-Chips and Inputs/Outputs (I/Os).
Background
  • Currently an academic faculty at the School of Integrated Circuits, Southeast University, Nanjing, China. Broadly interested in the architecture, micro-architecture, and design automation for emerging computing systems, with a particular focus on improving their safety, security, reliability, and timing-predictability.
Miscellany
  • Personal interests and other information are not provided.