Scholar
Samuel Pagliarini
Google Scholar ID: YQSZDq8AAAAJ
Carnegie Mellon University / Tallinn University of Technology
hardware security
ASIC
circuit reliability
CAD
VLSI
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Citations & Impact
All-time
Citations
927
H-index
17
i10-index
30
Publications
20
Co-authors
0
Contact
Email
pagliarini@cmu.edu
GitHub
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Publications
2 items
Security Analysis of Universal Circuits as a Mechanism for Hardware Obfuscation
2026
Cited
0
A Zero-overhead Flow for Security Closure
2025
Cited
0
Resume (English only)
Academic Achievements
Published papers in top venues including IEEE TCAD, TCHES, Asia CCS, ACM Computing Surveys, IEEE TCAS-II, and DATE
2025: Paper on secure layout synthesis published in IEEE TCAD
2024: Survey on FPGA-inspired obfuscation published in ACM Computing Surveys
2024: Awarded NSF grant for the US-EE-UA project on secure cryptographic hardware accelerators
Led or participated in major international projects including DARPA CRAFT and OMG, IARPA RAVEN, EU H2020 SAFEST, and NSF Neuromorphic Hardware
Supervised multiple PhD students to successful thesis defenses (e.g., Zain Ul Abideen, Felipe Almeida, Mohammad Eslami, Malik Imran)
Published a book on FPGA-like obfuscation in 2023
Co-authors
0 total
Co-authors: 0 (list not available)
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