Papers accepted in SysCon 2025, ICMRE 2025, ICICT 2025, VECOS 2024; Serving as technical program committee member for SysCon 2025.
Research Experience
PostDoctoral Fellow at Hardware Verification Group (HVG), Concordia University, since July 2023; Research Associate at System Analysis and Verification (SAVe) Lab, NUST-SEECS, from March 2019 to March 2020; Research Assistant at SAVe Lab, NUST-SEECS, from July 2013 to February 2019; Visiting Researcher at HVG, Concordia University, from September 2017 to February 2018.
Education
PhD from NUST-SEECS, supervised by Prof. Osman Hasan; PostDoctoral Fellow at Hardware Verification Group (HVG), Concordia University, under the supervision of Prof. Sofiène Tahar since July 2023.
Background
Research Interests: Formal Methods and their applications in Control Systems, Analog Circuits, Biological Systems, Robotics, Aerospace, Communication Systems, Cell Injection Systems, Transportation Systems, and Software Systems.