1. Paper 'Cypress: VLSI-Inspired PCB Placement with GPU Acceleration' won the Best Paper Award at ISPD 2025;
2. Paper 'ARIES: An Agile MLIR-Based Compilation Flow for Reconfigurable Devices with AI Engines' nominated for Best Paper at FPGA 2025;
3. Paper 'HLS Formal Verification' won the Best Paper Award at FPGA 2024;
4. Paper 'RapidLayout' won the Best Paper Award at ACM TRETS 2023;
5. Patent CN109658402B granted;
6. Selected as DAC Young Fellow.
Research Experience
1. NVIDIA Research, PhD Research Intern, Design Automation Research, Mentor/Manager: Anthony Agnesina, Chenhui Deng, Mark Ren, May 2024 — Aug 2024, Jan 2025 — May 2025;
2. Advanced Micro Devices, Compiler Intern, Advanced Compilers for Distribution and Computation (ACDC), Chief Technology Organization (CTO), Manager: Stephen Neuendorffer, May 2023 — Aug 2023;
3. Intel Labs, Exempt Tech Employee, Specification and Validation End-to-End (SAVE) Group, SCL/ADR/IL, Manager: Jin Yang, Sunny Zhang, Feb 2021 — Aug 2021;
4. Tsinghua University, Research Assistant, Nanoscale Integrated Circuits and System Lab (NICS-EFC), Advisor: Prof. Yu Wang, Nov 2019 — Aug 2021;
5. The University of Waterloo, Mitacs Research Intern, WatCAG, Advisor: Prof. Nachiket Kapre, Jul 2019 — Oct 2019.
Education
1. Cornell University, M.S./Ph.D. in Electrical and Computer Engineering, Advisor: Prof. Zhiru Zhang, Aug 2021 — Present;
2. Sun Yat-sen University, B.Eng. in Telecommunication Engineering, Advisor: Prof. Xiang Chen, Aug 2016 — Jun 2020.
Background
Research Interests: Electronic Design Automation, Domain-Specific Languages for hardware design and programming, and hardware accelerators. Field: Electrical and Computer Engineering.
Miscellany
Donated hair to Locks of Love to support children suffering from hair loss;
'Serving Multi-DNN Workloads on FPGAs' selected as Featured Paper of IEEE Trans. on Computers.