Scholar
Pasquale Davide Schiavone
Google Scholar ID: mfZQ9zUAAAAJ
EPFL, OpenHW Group
Microprocessor design
Internet-of-Things
Machine Learning
Arithmetic Circuits
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Citations & Impact
All-time
Citations
1,704
H-index
14
i10-index
18
Publications
20
Co-authors
10
list available
Publications
8 items
Enabling Ultra-Low-Power Always-On Feedforward Leakage Suppression Logic Circuits with FDSOI
2026
Cited
0
X-HEEP: An Open-Source, Configurable and Extendible RISC-V Platform for TinyAI Applications
2025
Cited
0
e-GPU: An Open-Source and Configurable RISC-V Graphic Processing Unit for TinyAI Applications
2025
Cited
0
Just TestIt! An SBST Approach To Automate System-Integration Testing
2025
Cited
0
Quadrilatero: A RISC-V programmable matrix coprocessor for low-power edge applications
2025
Cited
0
ARCANE: Adaptive RISC-V Cache Architecture for Near-memory Extensions
2025
Cited
0
Increasing the Energy-Efficiency of Wearables Using Low-Precision Posit Arithmetic with PHEE
2025
Cited
0
Scalable and RISC-V Programmable Near-Memory Computing Architectures for Edge Nodes
arXiv.org · 2024
Cited
1
Co-authors
7 total
Luca Benini
ETH Zürich, Università di Bologna
Davide Rossi
Associate Professor, University Of Bologna
Francesco Conti
Associate Professor, University of Bologna
David Atienza
Professor of Electrical and Computer Engineering, EPFL
Frank K. Gürkaynak
Senior Scientist, ETH Zurich
Simone Benatti
Associate Professor, University of Modena e Reggio Emilia
Maurizio Martina
Dipartimento di Elettronica e Telecomunicazioni, Politecnico di Torino
