Scholar
Andrew Boutros
Google Scholar ID: seNirV4AAAAJ
University of Waterloo
Citations & Impact
Citations
1,256
H-index
19
i10-index
26
Publications
20
Co-authors
71
list available
Resume (English only)
Academic Achievements
- 1. Our FPL’25 Double Duty paper proposing architecture modifications that allow the concurrent use of FPGA lookup tables and adder chains won the best paper award.
- 2. Our work on FPGA logic block modifications to enable the concurrent use of lookup tables and hardened carry chains is accepted for publication in FPL’25.
- 3. Our VTR 9 paper is accepted for publication in the ACM TRETS journal.
- 4. Our FPT’23 paper on 3D-stacked reconfigurable acceleration devices won the best paper award.
- 5. Our work on 3D-stacked reconfigurable acceleration devices is accepted for publication in FPT’23.
- 6. Our work on the architecture exploration flow of future RADs is accepted for publication in FPL’23.
- 7. Our book chapter on FPGA architecture is published as part of the Handbook of Computer Architecture by Springer Nature.
- 8. Our work extending the Koios suite of deep learning FPGA benchmark circuits is accepted for publication in TCAD.
- 9. Our work on placement optimization for FPGAs with embedded hard NoCs is accepted for publication as a full paper in FCCM’23.
- 10. Our work on flexible FPGA-based acceleration of NLP models (BERT, GPT) is accepted for publication in TACO.
- 11. Our journal paper on architecture and application co-design for new beyond-FPGA devices is accepted for publication in IEEE Access.
Research Experience
- Before joining the University of Waterloo, he was a researcher at Intel Labs and Intel’s Programmable Solutions Group (now Altera). He then established and led the Toronto office of MangoBoost, a Seattle-based startup developing data processing units for datacenter infrastructure acceleration.
Education
- Ph.D. in Electrical and Computer Engineering from the University of Toronto, supervised by Prof. Vaughn Betz
Background
- Research interests include efficient hardware acceleration of key applications (such as deep learning and networking) using FPGAs and other reconfigurable architectures, architecture of future FPGAs and beyond-FPGA reconfigurable acceleration devices, and applying machine learning techniques in FPGA computer-aided design tools for faster runtime and higher quality of results.
