Scholar
Vikram Jain
Google Scholar ID: uYVMSsEAAAAJ
Postdoc and Lecturer, SLICE/BWRC, UC Berkeley
Citations & Impact
Citations
556
H-index
9
i10-index
9
Publications
20
Co-authors
8
list available
Publications
Resume (English only)
Academic Achievements
- - Published several papers and posters in top conferences and journals such as ISSCC, JSSC, VLSI, DAC, DATE, ISLPED, ISCAS, TCAS-I, TVLSI, and TComp
- - Received the Solid-State Circuits Society (SSCS) Predoctoral Achievement Award for 2022-2023, the SSCS Student Travel Grant in 2022, and the Lars Pareto Travel Grant in 2019
- - Prestigious research fellowship from the Swedish Institute (SI) for 2016–2017 and 2017–2018 during his master’s program
Research Experience
- - Principal Engineer at TSMC, San Jose, working on efficient AI acceleration architectures and compute-in-memory design
- - Postdoctoral researcher at SLICE Lab and BWRC, University of California, Berkeley
- - Lecturer in the EECS department at UC Berkeley, teaching IC Design Project class and co-instructing Hardware for Machine Learning course
- - Visiting Researcher at IIS Laboratory, ETH Zurich, working on high-performance networks-on-chip for DNN platforms
Education
- - Ph.D. from KU Leuven MICAS Laboratories, focusing on energy-efficient heterogeneous systems for embedded machine learning (ML)
- - M.Sc. from Chalmers University of Technology, Gothenburg, Sweden, in embedded electronics systems design (EESD)
- - B.Tech. from Sathyabama Institute of Science and Technology, India, in Electrical and Electronics Engineering (silver medal)
- - Advisor Information: No specific advisor names mentioned
Background
- - Research Interests: AI/ML accelerators, RISC-V architecture, heterogeneous integration, Chiplets (2.5D and 3D), heterogeneous multi-core systems, network-on-chips, design space exploration, low-power digital design, hardware design automation, AI for chip design
- - Professional Field: Electrical and Computer Engineering
- - Brief Introduction: Incoming Assistant Professor at the ECE department, Purdue University in Fall 2026. Currently a Principal Engineer at TSMC, San Jose, working on efficient AI acceleration architectures and compute-in-memory design.
Miscellany
- - Seeking highly motivated prospective PhD students to join his team for Fall 2026 at the ECE department, Purdue University
