quantum circuit depth optimization

Noisy Intermediate-Scale Quantum (NISQ) hardware suffers from severe resource constraints—including noise, limited qubit count, restricted gate count, and shallow circuit depth—hindering practical deployment of quantum algorithms. Method: This work systematically investigates semantics-preserving quantum circuit optimization grounded in ZX-calculus. We propose the first comprehensive classification framework for ZX-based optimization techniques, unifying graph reduction, spider fusion, and the Steane algorithm to enable gate merging, redundant gate elimination, and circuit depth compression. Our approach further introduces multi-objective co-optimization, scalable algorithm design, and enhanced circuit extraction. Results: Experiments demonstrate significant reductions in circuit depth, single- and two-qubit gate counts, and logical error rates—substantially improving execution efficiency on NISQ devices. This work establishes a systematic methodology for ZX-calculus–driven quantum compilation and bridges combinatorial optimization with quantum computing research.

Quantum circuit fidelity is severely degraded by hardware noise, topology constraints, and compilation choices; yet the coupled impact of compiler strategies (qubit mapping, routing, optimization level) and hardware parameters (noise spectrum, connectivity, scale) remains poorly quantified. Method: We propose a noise-aware full-stack design space exploration (DSE) framework integrating Qiskit-based compilation modeling, hardware sensitivity analysis, fidelity prediction, and quantum error correction (QEC)-aware simulation. Contribution/Results: Our work is the first to quantitatively demonstrate that judicious selection of initial qubit layout and routing can suppress hardware errors more effectively than conventional error mitigation techniques. We further establish that hardware–software co-design remains critical even in QEC-enabled scenarios. Experiments across diverse noisy intermediate-scale quantum (NISQ) and prospective fault-tolerant architectures show an average 12.7% improvement in expected fidelity, alongside reductions in circuit depth and gate count. The framework delivers actionable mapping strategies and hardware configuration guidelines for both near-term noisy and future fault-tolerant quantum systems.

Quantum Circuit Born Machines (QCBMs) on Noisy Intermediate-Scale Quantum (NISQ) devices face a fundamental trade-off between expressive power and hardware feasibility in financial generative modeling. Method: We propose a large language model (LLM)-driven, hardware-aware ansatz design framework that integrates prompt engineering and iterative feedback to automatically generate shallow-depth, high-fidelity quantum circuits tailored to real-device constraints—including chip topology and noise profiles. Contribution/Results: Our approach incorporates KL-divergence-based evaluation, circuit depth optimization, and empirical validation on 12-qubit IBM quantum hardware, achieving superior generative performance and modeling accuracy over baseline methods. Crucially, this work introduces the first LLM-guided architecture search for QCBMs, enabling end-to-end, automated synthesis of deployable quantum generative models directly from hardware specifications.

Quantum neural networks (QNNs) for regression tasks suffer from manual, experience-driven architecture design, hindering scalability and reproducibility. Method: We propose Reduced Regressor—the first genetic algorithm–based automated QNN architecture search framework—jointly optimizing circuit depth, parametrized gate placement, and data encoding strategies. Crucially, we introduce a novel twelve-dimensional quantum circuit structural complexity metric integrated with meta-learning to enable high-fidelity performance prediction. Results: Evaluated on 26 nonlinear benchmark functions, the discovered QNNs achieve near-optimal regression accuracy with remarkably low parameter counts—on average requiring fewer parameters than 17 classical baselines. In meta-learning scenarios, architecture selection accuracy reaches 98.6%–100%. This work provides the first systematic empirical validation that lightweight QNNs can match or approach classical models’ regression performance with superior parameter efficiency, establishing their feasibility and practicality for real-world regression tasks.

High-precision numerical representations of QUBO coefficients severely degrade the efficiency of specialized hardware—particularly quantum annealers—due to excessive bit-width requirements. Method: We propose a branch-and-bound algorithm that uses dynamic range as a precision-complexity metric, the first such formulation to model dynamic range theory explicitly as the optimization objective for QUBO coefficient quantization. Our framework jointly optimizes precision compression and search efficiency while guaranteeing convergence and solution quality. Crucially, it requires no hardware modification—only input coefficient bit-width reduction via preprocessing. Results: Evaluated on real quantum annealing hardware, our method achieves 35–52% average bit-width compression, 1.8× throughput improvement, 2.3× energy-efficiency gain, and maintains optimal solutions with ≥99.2% fidelity.

To address poor scalability and challenging crosstalk suppression in large-scale superconducting quantum circuit parameter design, this paper proposes a graph neural network (GNN)-based “three-level scaling” optimization framework. The method introduces a novel supervised–unsupervised co-training paradigm: a medium-scale circuit is used to supervise the training of an evaluator, while an unsupervised designer generalizes the optimization to large-scale circuits. It is the first approach to jointly optimize single- and two-qubit gate frequencies—modeled as node and edge attributes on a circuit graph, respectively. Evaluated on an 870-qubit circuit, the framework reduces error rates by 49% compared to the state-of-the-art algorithm (achieving a 51% error reduction) and accelerates design time from 90 minutes to 27 seconds. The method achieves high accuracy, ultra-low latency, and strong scalability, establishing a new paradigm for automated superconducting quantum chip design.

This work addresses the intricate trade-offs among returns, risk, transaction costs, and constraints in multi-period dynamic portfolio optimization by proposing a sampling-based variational quantum algorithm tailored for near-term quantum hardware. The core innovations include an adaptive CVaR (Conditional Value-at-Risk) sampling schedule, a two-stage hybrid optimization strategy combining particle swarm optimization with the Nakanishi-Fujii-Todo optimizer, and two hardware-aware ansatz layouts: a data-guided coloring layout and a heavy-hexagon-native deep-chain layout. Experimental results on the 150-qubit ibm_quebec processor demonstrate that the heavy-hexagon-native deep-chain layout achieves superior performance in both objective value and CVaR tail metrics, establishing an effective paradigm for implementing variational algorithms on noisy intermediate-scale quantum devices.

This work addresses the optimization challenges posed by barren plateaus in parametrized quantum circuit training by introducing the first four-player potential game framework that jointly optimizes trainability, non-stabilizerness, task performance, and hardware overhead. The quantum circuit is modeled as a directed acyclic graph, wherein each player performs append, delete, retype, or reconnect operations to seek an ε-Nash equilibrium. An efficient search algorithm based on block-coordinate ε-Nash residuals evolves circuits within a constrained action space. Experiments on MaxCut K₄ and LiH tasks demonstrate that the generated circuits simultaneously achieve high performance, significantly reduced gate counts, enhanced non-stabilizerness, and effective barren plateau avoidance. On a 2×2 grid topology, the approach repeatedly approaches the theoretical potential upper bound, revealing the underlying Pareto trade-offs among the multiple objectives.

This study addresses the industrial applicability of quantum computing to combinatorial optimization problems. It provides a systematic review of mainstream quantum optimization approaches—including quantum annealing, the Quantum Approximate Optimization Algorithm (QAOA), Quantum Reinforcement Learning (QRL), and Quantum Generative Modeling (QGM)—and, for the first time, aligns these methods precisely with real-world domains such as logistics, finance, and telecommunications. Leveraging authoritative benchmarking platforms like QOBLIB and QUARK, the work evaluates the engineering maturity and empirical evidence of quantum advantage across these algorithms. Findings indicate that quantum annealing currently offers the highest practical utility, QAOA demonstrates feasibility on NISQ devices, and QRL and QGM represent promising high-impact directions for future development. This research establishes a comprehensive evaluation framework and strategic roadmap for the industrial deployment of quantum optimization technologies.

This work addresses the tension between expressivity and trainability in variational quantum circuits, where highly expressive ansätze often suffer from barren plateaus, while structures avoiding this issue are frequently classically simulable. The authors propose a Stacked Linear Combination of Unitaries (S-LCU) ansatz that systematically balances trainability and computational complexity through a single tunable parameter—the number of layers $l$. Constructed from fermionic Gaussian unitaries, the S-LCU enables analytical derivation of a lower bound on the variance of the loss landscape, proven to be $\Omega(1/(n k^{3l}))$. Crucially, its classical simulation cost scales as $O(k^{2l} n^3)$, whereas the quantum gate complexity grows only as $O(l k n^2)$, thereby achieving a tunable trade-off between quantum advantage and trainability.

This work addresses the problem of synthesizing quantum circuits for a given unitary operator with the minimal number of T gates. It introduces, for the first time, a formulation of the minimal-T-count synthesis problem as a continuous optimization problem amenable to numerical solution, combined with a binary search strategy to efficiently approximate the optimal T count. To enhance scalability, the approach further incorporates a circuit partitioning technique that substantially extends the range of solvable instances. The method not only reproduces known optimal T counts for small-scale circuits but also surpasses existing limits on circuit size that can be practically optimized, thereby offering a promising new pathway toward the efficient compilation of large-scale quantum circuits.