remote device management

To address low FPGA SoC computational resource utilization and inflexible functional reconfiguration in 5G/6G radio units, this paper proposes a hierarchical, data-driven micro-orchestrator framework supporting event-triggered dynamic partial reconfiguration and hardware resource virtualization. The framework automates the FPGA functional lifecycle management, enabling fine-grained, context-aware, function-level on-demand reconfiguration. Its effectiveness is validated in edge computing applications, particularly computer vision. Compared to conventional static deployment, the proposed approach achieves a measured 42% improvement in hardware resource utilization and reduces reconfiguration latency to under 10 ms, thereby significantly enhancing system real-time responsiveness. This work delivers a lightweight, efficient, and adaptive resource management layer for reconfigurable hardware infrastructures in edge intelligence scenarios.

To address the low efficiency and error-proneness of manual development and integration of software components in embedded systems, this paper proposes an Abstract Syntax Tree (AST)-driven Retrieval-Augmented Generation (RAG) method for fully automated, zero-intervention generation and formal verification of microcontroller Hardware Abstraction Layer (HAL) code. Focusing on the STM32F407 GPIO module, the approach integrates AST-based semantic analysis, RAG-enabled dynamic knowledge retrieval, static code verification, and HAL framework adaptation to ensure syntactic correctness, semantic consistency, and platform compatibility. Experimental evaluation demonstrates that the generated HAL code is functionally complete, directly compilable and flashable, and passes comprehensive functional testing on real hardware across all operational scenarios, achieving 98.7% accuracy. This work establishes the first end-to-end pipeline for automated HAL code generation coupled with formal verification in embedded systems.

Dynamic security analysis of MCU firmware faces significant challenges in constructing scalable, high-fidelity emulation environments due to the extreme heterogeneity of peripheral hardware. Method: This paper proposes FlexEmu, a novel framework that abstracts MCU peripheral hardware implementations into a set of finite structural primitives and establishes a unified semantic model to capture functional equivalence across peripheral classes, enabling automated peripheral modeling and emulator generation. FlexEmu achieves high-fidelity emulation through structural primitive extraction, semantic-driven configuration parsing, and behavior-aware simulation. Results: Evaluated across 12 peripheral types, 15 MCU platforms, and 90 firmware samples, FlexEmu achieves a unit test pass rate of 98.48%. Integrated with fuzz testing, it discovers 10 previously unknown vulnerabilities across three mainstream RTOSes. FlexEmu substantially enhances both the practicality and scalability of dynamic firmware analysis.

To address the lack of systematic continuous verification and secure release mechanisms in open-source hardware design, this paper pioneers the systematic adaptation of software CI/CD paradigms to the hardware domain, proposing a general-purpose framework for automatic hardware specification mining and continuous deployment. Methodologically, it integrates HDL static analysis, machine learning–driven specification inference, formal verification, and cloud-native automated pipelines, implemented in the prototype system Myrtha. Key contributions include: (1) the first CI/CD architecture supporting continuous hardware specification generation, verification, and release; (2) a scalable, automated specification mining mechanism that overcomes traditional manual modeling bottlenecks; and (3) substantial improvements in quality assurance, experimental reproducibility, and cross-team collaboration efficiency for open-source hardware development.

This work addresses the challenge of short embedded-system lifecycles and inflexible driver updates in industrial automation, hindering timely compliance with evolving regulations and market demands. To this end, we propose Wasm-IO—a novel framework that pioneers the adaptation of WebAssembly (Wasm) to safety-isolated peripheral I/O execution. Wasm-IO introduces a first-of-its-kind Wasm-based interrupt priority extension model enabling deterministic, time-isolated interrupt handling, coupled with platform-agnostic inlined driver support and synchronous I/O abstractions to enable standards-compliant driver hot-swapping. Leveraging lightweight containerization, interrupt virtualization, and real-time scheduling, it significantly reduces I/O latency and runtime overhead. Experimental evaluation demonstrates cross-platform portability, strong spatial and temporal isolation, and practical feasibility on real industrial hardware. Wasm-IO establishes a secure, flexible, and sustainably evolvable paradigm for driver execution in industrial embedded systems.

This study addresses the challenges of high latency, unstable concurrency, and security risks faced by large language model (LLM) agents in automating asset lifecycle management within Industry 4.0. The authors propose a Plan-then-Execute architecture that generates verifiable workflow graphs and integrates a topology-aware parallel scheduling mechanism to enable controlled inference overlap while ensuring functional correctness and security. Key technical contributions include topological-sort-based multi-agent scheduling, structured context pruning, dependency-aware concurrency control, and graceful degradation under fault injection. Evaluated on the AssetOpsBench benchmark, the system reduces median end-to-end latency by 1.6× (up to 1.8× for highly parallel tasks) and cuts inference overhead by approximately 30% through context pruning, all while maintaining stable task completion rates and output quality.

This work addresses the inefficiencies and semantic inconsistencies arising from separately implementing driver and monitor programs in traditional hardware module testing. To overcome this, the authors propose a domain-specific language (DSL) tailored to hardware communication protocols, which enables the unified specification of both driver and monitor logic through an imperative syntax, thereby ensuring their semantic consistency for the first time. Building upon this DSL, they develop a prototype tool that leverages waveform parsing and transaction-level trace inference techniques to accurately reconstruct protocol-compliant transaction sequences from raw signal waveforms. Experimental results demonstrate that the approach significantly improves development efficiency, with further validation planned on real-world interconnect protocols such as Wishbone and AXI-Stream.

This work proposes a unified, stateful agent-based execution infrastructure for integrating large language models with electronic design automation (EDA) tools. Addressing the limitations of existing stateless scripting or request-response paradigms—which hinder iterative optimization in production environments—the architecture introduces a managed gateway interface coupled with persistent EDA tool instances. This enables, for the first time, an execution layer that supports state reuse, rollback, and collaborative iteration. By employing a structured request/response mechanism, the system facilitates state-preserving interactions with heterogeneous EDA tools. The approach is validated through two commercial use cases: post-routing timing engineering change orders (ECOs) and standard cell sublibrary optimization, where it successfully orchestrates multi-step analysis and refinement workflows, demonstrating its effectiveness and practicality in agent-driven EDA automation.

This work addresses the challenges faced by large language model (LLM) agents operating over flat tool registries—namely, combinatorial explosion in decision space, context saturation, and degraded routing accuracy. To overcome these limitations, the authors propose a skill-tree-based hierarchical architecture that separates routing logic at internal nodes from execution at leaf nodes. Inspired by pushdown automata, the framework incorporates a LIFO stack-frame memory model and a lazy capability discovery mechanism, enabling isolated execution paths and scalable context management. The approach supports manifest-driven single-step execution loops and formal state modeling, significantly improving routing accuracy while reducing memory footprint and prompt costs under conditions of tool proliferation, multi-step workflows, and prompt exposure. This design meets enterprise-grade requirements for isolation and scalability.

This work addresses the challenge of achieving bounded, verifiable, and deterministic coordination in safety-critical real-time autonomous systems operating under uncertainty. It proposes a hardware-enforced semantic coordination architecture that, for the first time, directly maps a topic-based communication space Petri net (TB-CSPN) coordination mechanism onto the FPGA hardware layer. By leveraging hardware primitives to construct a native semantic coordination layer, the approach ensures deterministic execution of time synchronization, semantic gating, authorization constraints, and bounded coordination behaviors—without relying on software mediation. The design decouples low-level interaction management from high-level semantic reasoning, thereby preserving software adaptability while guaranteeing hardware-level reliability. This integration yields a highly dependable real-time system architecture with formally verifiable safety assurances, deterministic coordination, and bounded latency.