resource-aware mapping

Addressing the challenges of computationally expensive compilation and difficulty in determining the minimum initiation interval (II) for loop mapping on coarse-grained reconfigurable arrays (CGRAs), this paper proposes a SAT-based formal compilation optimization method. The core contribution is the Kernel Mobility Schedule—a novel scheduling mechanism that uniformly encodes all valid dataflow graph (DFG) mappings onto the target CGRA topology as a Boolean satisfiability (SAT) problem. It jointly models architectural constraints—including resource availability, interconnect connectivity, and timing—and modulo scheduling semantics to enable II-driven, end-to-end mapping search. Experimental evaluation demonstrates that our approach reduces average compilation time by 37% while achieving a 12.6% smaller II and higher mapping quality, significantly outperforming state-of-the-art methods.

To address the challenge of jointly optimizing I/O, memory, and parallelism in deep learning inference, this paper proposes a hardware-aware co-mapping framework for data and instructions. The method unifies the scheduling of data and instruction flows, integrating fine-grained message passing, weight residency and reuse, intra-array multicast, and staged reduction—enabling streaming on-chip execution on a message-based programmable architecture. Experimental results demonstrate that, on VGG-19, the design achieves 88–92% computational utilization, generates over 97% of messages on-chip, performs 89% of data transfers on-chip, reduces per-layer data movement by up to 100 MB, and delivers computation throughput exceeding 1 TFLOP/s. These improvements significantly alleviate reliance on host control, off-chip I/O, and DRAM access.

Manual pragma configuration in high-level synthesis (HLS) suffers from low efficiency and an exponentially large search space. Method: This paper proposes the first nonlinear programming (NLP)-based automated pragma insertion framework, jointly optimizing loop-level pragmas—including pipelining, function unit replication, and data caching. It innovatively models discrete pragma configurations as continuous, differentiable variables and constructs analytical performance/resource models with theoretical lower-bound guarantees, solved globally via NLP. Integrated with pragma semantic analysis and the Merlin compiler, and augmented by design-space pruning, the framework explores billion-scale configurations within seconds to minutes. Contribution/Results: Experimental evaluation shows kernel performance approaching hand-tuned implementations, resource estimation error <8%, and latency lower-bound error ≤12%.

This paper addresses the efficient mapping of compute-intensive loops onto coarse-grained reconfigurable arrays (CGRAs), targeting minimization of the initiation interval (II). We propose a SAT-based modulo scheduling approach, whose core innovation is Kernel Movement Scheduling (KMS)—a novel scheduling representation that uniformly encodes mapping constraints as Boolean logic formulas, thereby overcoming the search limitations inherent in conventional graph-based algorithms. Integrating modulo scheduling theory, dataflow graph analysis, and iterative feasibility verification, our method systematically generates and validates legal mappings for a given II. Experimental evaluation demonstrates that our approach outperforms state-of-the-art techniques on 47.72% of benchmarks, achieving lower IIs and uncovering several previously unrecognized valid mappings.

Addressing three key challenges in CPU microarchitecture design space exploration (DSE)—degraded surrogate model accuracy and scalability, inefficient acquisition strategies, and poor interpretability—this paper proposes AttentionDSE, the first DSE framework integrating attention mechanisms. It unifies high-accuracy performance prediction with real-time bottleneck identification via interpretable, dynamic mapping from architectural parameters to performance contributions. Methodologically, AttentionDSE synergistically combines attention-based modeling, multi-objective optimization, and Pareto frontier search, enabling adaptive analysis under design modifications. Evaluated on the SPEC CPU 2017 benchmark suite, it reduces exploration time by over 80% and improves Pareto hypervolume by 3.9%, while significantly outperforming state-of-the-art approaches in both prediction accuracy and scalability.

This work addresses the combinatorial explosion in GEMM mapping space on spatial accelerators, which hinders efficient discovery of globally optimal mappings. For the first time, the authors derive an analytical energy model from first principles using geometric abstraction, formulating mapping selection as an integer optimization problem subject to hardware constraints. This approach enables exact energy evaluation and global optimum search with O(1) complexity. Evaluated across diverse accelerators and large language model prefill tasks, the method achieves 2.24–4.24× improvement in energy-delay product and 3.83–73.6× faster solution times compared to state-of-the-art mappers.

This work proposes a novel interior-point method implementation that overcomes the limitations of traditional approaches, which rely on sparse linear solvers and struggle to leverage accelerator hardware such as GPUs efficiently. By reformulating the sparse linear systems into manageable dense problems, the method entirely eliminates dependence on sparse solvers, enabling the entire optimization pipeline to execute efficiently on accelerators. Built upon the performance-portable programming models Umpire and RAJA, the approach supports cross-platform deployment. Its effectiveness is demonstrated on canonical sparse nonlinear optimization problems, including optimal power flow in power systems, achieving GPU utilization exceeding 90%. This study establishes a new paradigm and benchmark for accelerator-native interior-point methods.

This work addresses the performance limitations of RISC-V multi-lane chained vector processors, which struggle to approach theoretical peak performance due to bottlenecks in memory bandwidth, control dependencies, and operand forwarding. Building upon the open-source RVV processor Ara, the authors propose a microarchitectural co-optimization methodology tailored for multi-lane chained execution. By employing an ideal steady-state execution model to precisely identify critical bottlenecks, they introduce conservative dependency management enhancements, optimized memory transaction scheduling, and restructured result propagation pathways—all without increasing hardware resources. The resulting optimized system, Ara-Opt, achieves an average speedup of 1.33× under identical configurations and closes 12.2% of the performance gap relative to the roofline model on average. Notable improvements are observed in key kernels, with scal, axpy, ger, and gemm accelerating by 2.41×, 1.60×, 1.52×, and 1.42×, respectively.

This work addresses the challenge of sustaining Exascale performance on heterogeneous supercomputing systems under real-world deployment constraints. Conducted on the Aurora system through three rounds of HPL and HPL-MxP benchmarking, the study proposes a suite of optimizations—including deterministic locality-aware resource mapping, explicit CPU-GPU pipelining, mixed-precision co-scheduling, and a hybrid point-to-point/collective communication fault-tolerance strategy—to effectively mitigate large-scale synchronization stalls. Leveraging hardware features such as Intel discrete GPUs, CPU-direct networking, Slingshot-11 interconnects, and AMX acceleration, the approach boosts FP64 performance from 0.585 to 1.01 EF/s and achieves 11.64 EF/s on HPL-MxP, demonstrating an 11.5× speedup over FP64 and validating the efficacy of hardware-software co-design at extreme scale.

This work addresses the challenge of efficiently exploring the vast and physically constrained design space of cross-layer heterogeneous systems to support mixed AI and high-performance computing (HPC) workloads. To this end, the authors propose CHASE, a novel framework that decouples hardware architecture design from task mapping. CHASE leverages hierarchical type graphs for system modeling, a topology-aware mapper, and a telemetry-guided optimizer to enable application-driven architecture search under deployment constraints. Experimental results demonstrate that CHASE achieves geometric mean speedups of 6.20× and 2.12× on sparse computing and large language model workloads, respectively, while reducing mapping time by 60.5% on average and converging to near-global-optimal solutions within 64 iterations.