simd vectorization

Existing long-vector ISAs struggle to fully exploit ultra-wide SIMD resources in in-memory computing, particularly under multi-directional parallel workloads, due to inherent limitations of one-dimensional memory access and execution models—resulting in suboptimal performance and energy efficiency. This paper targets mobile in-cache computing and proposes the Multidimensional Vector Extension (MVE): the first ISA extension to directly expose multidimensional data parallelism at the instruction level, supporting multidimensional strided and random memory access, dimension-wise masking, and cache-geometry-aware abstraction to maximize SIMD utilization. MVE is designed for compatibility with both RISC-V and Arm architectures. Evaluation on mobile data-parallel workloads demonstrates an average 2.9× speedup and 8.8× energy-efficiency improvement, with only a 3.6% area overhead.

Modern compilers (e.g., LLVM, GCC) struggle to fully exploit SIMD parallelism (e.g., AVX, RVV) due to complex control-flow analysis, limited IR expressiveness, and fragmented vectorization pipelines. This work proposes a scalable vectorization framework: first, it extends LLVM IR with two novel representations—Structured IR (SIR) to explicitly encode control-flow structures, and Vector IR (VIR) to precisely model data dependencies; second, it integrates CFG reconstruction, fine-grained dependency analysis, and cross-IR pattern matching to improve both the accuracy of vectorization opportunity detection and the completeness of the search space. Experimental evaluation on standard benchmarks demonstrates performance improvements of up to 53% over LLVM and 58% over GCC, while significantly enhancing vectorization coverage and end-to-end compilation efficiency.

To address low similarity-search efficiency and limited acceleration from approximation algorithms under frequent updates in vector databases, this paper proposes PDX—a vertical data layout that partitions vectors by dimension, enabling automatic scalar vectorization and tight-loop multi-vector computation within blocks. We introduce PDX-BOND, the first preprocessing-free dynamic dimension pruning strategy, which restores and enhances the effectiveness of pruning algorithms (e.g., ADSampling, BSA) in approximate search, achieving 2–7× speedup. Compared to SIMD-optimized horizontal layouts, PDX delivers an average 40% speedup in both exact and approximate search while natively supporting high-frequency insertions, deletions, and updates. The core innovations are (1) a dimension-wise vertical blocking architecture and (2) the PDX-BOND pruning mechanism—jointly ensuring high performance, broad applicability, and update friendliness.

To address the challenges of large die area, low energy efficiency, and limited throughput in existing RISC-V vector processors, this work designs and open-sources the first high-performance lane-based scalar-vector tightly coupled processor compliant with the RISC-V V 1.0 vector extension. We propose a PPA (Power-Performance-Area)-driven scalar-vector co-designed microarchitecture, innovatively integrating a customized floating-point unit (FPU) pipeline with an optimized register file organization to overcome throughput and energy-efficiency bottlenecks inherent in conventional RVV implementations. Experimental results demonstrate a 15% reduction in silicon area and a 6% improvement in instruction throughput compared to prior RVV vector engines. Moreover, the FPU utilization for key kernel functions reaches 98.5%, significantly enhancing processing efficiency for data-parallel workloads.

To address hardware bottlenecks in energy-efficient floating-point computation, this work proposes Spatz—a compact 64-bit floating-point vector processor based on the RISC-V Zve64d extension—along with a scalable dual-core cluster architecture. Innovatively, it employs a minimal 2 KiB latch-based vector register file and a shared scratchpad memory, substantially reducing area and power overhead in GlobalFoundries’ 12LPP process. The proposed FPU-intensive cluster achieves 95.0% FPU utilization under realistic workloads such as 2D convolution, delivering a peak performance of 15.7 DP-GFLOPS at 1 GHz and 0.80 V. It attains an energy efficiency of 95.7 DP-GFLOPS/W overall, improving to 99.3 DP-GFLOPS/W and 171 DP-GFLOPS/W/mm² under convolution workloads—representing a 30% energy-efficiency gain over scalar-core clusters of equivalent die area.

Existing matrix instruction set architectures (ISAs) suffer from low efficiency on small, irregular matrices in GEMM operations and lack flexibility for diverse data formats and deep learning workloads (e.g., convolutions, Transformers). This paper proposes a novel decoupled matrix ISA that fully separates instruction-set specification from microarchitectural implementation. Our design supports three-dimensional vectorization over M, N, and K dimensions, maintains backward compatibility with existing vector ISAs, and introduces only a minimal set of new instructions and a 64-bit control register—enabling low-overhead, flexible extensibility. Key microarchitectural techniques include Matrix Tiling Extension (MTE), vector register reuse, dynamic tiling configuration, and SIMD co-execution. Experimental evaluation demonstrates a 1.35× speedup in GEMM performance over the state-of-the-art matrix ISA and significant improvements in computational efficiency across core kernels of mainstream AI models.

This work addresses the challenge of efficiently generating vector-length-agnostic (VLA) machine learning code for scalable vector instruction sets such as Arm SVE, where unknown vector lengths at compile time hinder traditional compilers. The authors present the first end-to-end VLA support in MLIR/IREE, introducing a vector-length-aware compact data layout and unifying dynamic tiling, operator fusion, and scalable vectorization within a single compilation framework. Evaluated on Arm CPUs, the generated SVE code achieves up to 1.45× speedup over IREE’s NEON implementation, outperforms multiple frameworks in the PyTorch ecosystem, and demonstrates strong scalability with increasing vector lengths in simulation, effectively balancing performance and hardware portability.

This work addresses the widespread lack of correctly rounded results in high-performance vector math libraries, which undermines bit-level reproducibility across platforms. The authors propose a unified framework that integrates SIMD parallelism with correctly rounded algorithms to efficiently implement multiple single-precision, single-input mathematical functions on CPUs and, for the first time, extend this approach to GPUs. They also provide a prototype implementation for double-precision functions. This research lays the foundation for the first cross-platform vector math library supporting correct rounding, with a planned public release by mid-2026, significantly advancing reproducibility and precision guarantees in numerical computing.

Traditional tightly coupled RISC-V vector processors struggle to sustain high-throughput execution due to bottlenecks in instruction supply, scalar latency, and dependency handling. This work proposes SEAM-V, a novel architecture that decouples computation at the task level, employs localized instruction delivery, and generates VLIW-style execution packet (EP) streams. By explicitly maintaining EP context in the backend, SEAM-V enables intra-packet hazard suppression and prefetching. The design integrates hybrid decoupled scheduling, EP serialization, request-bound prefetching, and dynamic resource management to preserve dynamic dependency and memory ordering correctness while enabling intra-packet optimizations and limited inter-packet vector overlap. Evaluated on 17 representative kernels, SEAM-V achieves a geometric mean speedup of 1.34× over Ara, with near 3× acceleration on one-dimensional variable-length vector kernels at AVL=32.

This work addresses the challenge of automatically selecting the highest-performing FFT implementation among mathematically equivalent variants on a given hardware platform, which requires modeling context-dependent effects such as cache state transitions between instructions. The authors formulate FFT optimization as a shortest-path problem on a directed acyclic graph and introduce a context-aware graph model in which nodes encode the type of preceding operations, explicitly capturing dependencies like cache warm-up—an aspect overlooked by conventional dynamic programming approaches. Leveraging Dijkstra’s algorithm for graph traversal, combined with empirical SIMD instruction cost measurements and NEON performance profiling, the method achieves 29.8 GFLOPS on an Apple M1 processor, outperforming a pure radix-2 implementation by 5.2× and surpassing context-agnostic strategies by 34%. The approach also uncovers highly efficient scheduling sequences, such as R4→R2→R4→R4→Fused-8.