buffer management

Memory contention among mixed-criticality tasks on memory-constrained edge devices degrades real-time performance and throughput. Method: We propose a dynamic memory allocation strategy balancing real-time guarantees and throughput. We first identify system-level long stalls—caused by page swapping under high memory pressure—and design a PSI (Pressure Stall Information)-based latency quantification model and long-stall detection mechanism. Our approach reserves memory for soft real-time tasks with fine-grained precision, proactively discards stalled non-real-time tasks to reduce interference, and leverages periodic task characteristics for adaptive, fine-grained memory scheduling. Contribution/Results: Under stringent conditions where available memory is only 60% of peak demand, our method achieves a 97.13% deadline satisfaction rate for soft real-time tasks and improves throughput of non-real-time applications by up to 22.32×, demonstrating significant gains in both timeliness and resource efficiency.

The widening gap between CPU and memory access latency poses a fundamental challenge to database performance. Method: This paper systematically surveys four decades of buffer management evolution, analyzing classical algorithms (e.g., LRU-K, 2Q, LIRS, ARC), ML-enhanced approaches, and memory-disaggregated architectures (NVM-aware hierarchies, RDMA-decoupled designs). It introduces the first holistic, time-spanning analytical framework for buffer management evolution and proposes a novel cross-layer adaptive paradigm integrating ML-driven policy learning with eBPF-based kernel extensibility. Contribution/Results: Grounded in empirical analysis of 50+ top-tier conference papers and industrial systems (Linux, PostgreSQL, Oracle), the work distills core design trade-offs and identifies key challenges—including cache coherence across heterogeneous memory tiers, low-overhead decision-making, and OS–DBMS co-design—along with concrete research directions toward scalable, adaptive buffer management.

In NUMA systems, poor coordination between the CPU scheduler and memory manager leads to thread–page-table placement mismatches. This paper proposes a hardware–software co-design optimization framework to address this issue. Our approach introduces: (1) the first joint thread and page-table placement mechanism; (2) differentiated migration and on-demand copying policies for data pages versus page-table pages; and (3) memory bandwidth throttling coupled with hardware performance counter–driven QoS feedback control to suppress cross-socket coherence overhead. Implemented as a Linux kernel module, the solution requires no application modifications. Experimental evaluation demonstrates that, compared to state-of-the-art approaches, our method reduces CPU execution cycles by 2.09× and page-table traversal overhead by 1.58×, significantly improving NUMA locality and scalability.

To address severe contention and scalability bottlenecks caused by fetch-and-add operations on a single memory location under high concurrency, this paper proposes Aggregating Funnels—a novel mechanism that distributes atomic operations across multiple memory locations to enable cross-location batch aggregation and decoupled result computation. Our approach leverages dual-location coordinated batching, lock-free concurrency control, and fine-grained memory layout optimization, building an efficient aggregation path directly atop hardware-supported fetch-and-add instructions. Unlike conventional single-point or combining funnels, Aggregating Funnels overcomes fundamental scalability limits inherent in prior designs. Experimental evaluation demonstrates significantly higher throughput compared to state-of-the-art Combining Funnels. When integrated into mainstream concurrent queues, it delivers substantial end-to-end performance improvements by eliminating critical serialization bottlenecks.

This work addresses the high analytical latency and severe resource contention in HTAP systems caused by traditional ETL pipelines, which entail frequent data movement. To overcome these limitations, the authors propose offloading data transformation logic to an intelligent storage layer that leverages near-data or in-storage computing capabilities to perform format conversion and preprocessing directly at the storage tier. This approach eliminates the overhead of data migration and significantly reduces interference with foreground transactional workloads, thereby enhancing both the performance and real-time responsiveness of analytical queries. Experimental results demonstrate that the proposed architecture achieves a highly reusable, low-latency data processing paradigm under mixed workloads across multiple execution engines, offering an efficient and scalable storage-compute co-design for HTAP systems.

This study investigates the scalability and performance of process and thread schedulers under memory-intensive workloads in multi-core shared-memory systems, focusing on a 3D tensor row-sorting task. The authors design and evaluate several scheduling strategies: on the thread side, an AIMD-based adaptive chunking mechanism inspired by TCP congestion control is introduced, coupled with exponential weighted moving average to dynamically adjust concurrency; on the process side, a bounded prolific/collective model is employed alongside one-to-one, one-to-many, and many-to-many pipelined communication patterns to enable flexible task distribution. Experimental results on a 24-core x86-64 platform demonstrate that thread-level scheduling consistently outperforms process-level scheduling, with dynamic and guided strategies achieving the best performance, while the many-to-many pipeline exhibits superior scalability for large-scale tasks.

This work addresses the high metadata overhead and serialization bottlenecks in Linux buffered reads under large-buffer scenarios, where fine-grained page cache operations impede the full utilization of modern parallel SSD throughput. To overcome this limitation, the authors propose a multi-stage read stack architecture that treats large-range reads as a single unit, decoupling page cache management from I/O scheduling. By introducing staged execution, proactive user-page fault handling, reordered and opportunistic parallel data copying, and optional parallel I/O submission, the design enables batched, asynchronous, and parallelized read paths. Implemented atop Linux 6.6.58, the approach achieves up to a 6.56× bandwidth improvement in MiB-scale fio reads, reaches 36.87 GiB/s (4.44× speedup) for 128 MiB random reads on a five-drive NVMe RAID0 array, and accelerates DuckDB/Parquet queries by 1.80–2.15× and ExecuTorch model loading by 3.17–3.61×.

Existing burst buffer file systems suffer from performance degradation due to rigid, fixed data layouts that fail to adapt to diverse application I/O behaviors. This work proposes Proteus, a system that treats data layout as a first-class optimization target by integrating static code analysis with lightweight runtime probes to reconstruct an application’s I/O semantic intent during a single pre-execution pass. Guided by a large language model, Proteus makes layout decisions without requiring training or intrusive profiling. Evaluated on representative HPC workloads, Proteus achieves a layout decision accuracy of 91.30% and delivers speedups of up to 3.24× in write-intensive scenarios and 2.9× in metadata-intensive workloads.

Shared state profoundly influences the performance and fault tolerance of stream processing, service-oriented, and continual learning systems, yet existing approaches often treat access control, hardware-aware execution, memory management, and long-term evolution in isolation. This work reframes state management as a runtime control problem and introduces a contract-driven blueprint centered on state objects, control planes, coupling paths, evaluation boundaries, and pending contracts. Building upon this foundation, we develop a unified analytical framework encompassing state-access scheduling, state-aware execution, and state evolution reuse. Through systematic scheduling, runtime control, and cross-layer coupling analysis, our approach identifies critical anti-patterns and advances a perturbation-aware evaluation paradigm, thereby establishing both theoretical foundations and practical design guidelines for state control in distributed systems.

This work addresses performance inconsistency and global I/O throttling failure in disaggregated storage clusters caused by cross-generational heterogeneous hardware and skewed access patterns. To this end, the authors propose IORM, a multi-stage distributed I/O resource manager featuring four key innovations: a hardware-transparent I/O accounting mechanism, a datasheet-based hardware-aware cost model, a quantum throttling policy supporting micro-bursts and credit carryover, and a distributed adaptive feedback controller capable of dynamically reallocating quotas. Experimental evaluation demonstrates that IORM supports 100 concurrent tenant volumes on an 8-node cluster, achieves throttling error below 5% under extreme sequential access skew, eliminates tenant interference entirely, and restores full throughput within 15 seconds following a storage node failure.