cache contention analysis

This paper addresses the long-standing challenge of quantitatively analyzing non-LRU cache replacement policies—such as FIFO and MRU—under arbitrary associativity and microarchitectural timing anomalies. We propose the first unified analytical framework for this problem. Methodologically, we introduce the novel concept of *block competitiveness*, enabling systematic transfer of LRU persistence analysis to non-LRU policies, and integrate worst-case execution time (WCET) analysis techniques to overcome the infeasibility of conventional approaches under timing anomalies. Our contributions are threefold: (1) the first rigorous, block-level competitiveness modeling for FIFO and MRU; (2) high-precision quantification of cache behavior across arbitrary cache ways and timing-anomalous microarchitectures; and (3) empirical validation on the TACLeBench benchmark suite, demonstrating accuracy approaching that of LRU-based analysis while ensuring both theoretical soundness and engineering deployability.

This work addresses key challenges in Profile-Guided Optimization (PGO): high sampling overhead, poor adaptability to dynamic inputs, and weak cross-architecture portability. We systematically survey and restructure the PGO technical landscape, proposing the first multi-dimensional classification framework for PGO—explicitly identifying three core research directions: low-overhead profiling, dynamic workload adaptation, and cross-architecture profile migration. Our approach unifies instrumentation- and sampling-based analysis, enabling compiler- and linker-time collaborative optimization in GCC and LLVM across heterogeneous targets including x86 and ARM. Empirical evaluation on standard benchmarks demonstrates an average performance improvement of 12.3%, while reducing profiling overhead to under 0.8%. These results significantly enhance the industrial deployability and generalization capability of PGO.

Traditional approaches struggle to provide deep visibility into the internal behavior of the gem5 simulator. This work proposes a non-intrusive, lightweight runtime call-stack analysis framework that, for the first time, treats the simulator’s own execution path as a novel lens for understanding simulated system behavior. Built upon the Linux perf_event interface, the framework enables parallel sampling, real-time symbol resolution, and hierarchical call-tree aggregation, with support for component-level customizable analysis. Experimental results demonstrate its effectiveness in uncovering performance bottlenecks in TimingSimpleCPU and identifying deadlock and livelock issues within the Ruby memory system—capturing critical behavioral characteristics that conventional statistical methods fail to detect.

Accurate characterization of microarchitectural behavior using hardware performance counters is hindered by ambiguous specifications, opaque designs, and multiplexing-induced noise, impeding experts’ ability to validate hypotheses. This work proposes CounterPoint, a framework that for the first time systematically integrates formal microarchitectural models—represented as μ-path decision diagrams—with noisy performance counter data. By comparing multidimensional confidence regions derived from the model against observed hardware events, CounterPoint automatically detects inconsistencies and pinpoints potential undocumented microarchitectural features. Applied to Intel Haswell’s memory management unit, the approach successfully uncovers several previously undisclosed mechanisms, including a load-store queue–side TLB prefetcher, a mergeable page table walker, and an abortable page table walk capability.

Accelerator Design Language (ADL) compilers suffer from unpredictable hardware performance due to the semantic gap between high-level abstractions and low-level implementations, compounded by reliance on heuristic optimizations. This work introduces Petal, the first tool enabling cycle-accurate, interpretable performance analysis for Calyx-based accelerators. Petal bridges the abstraction gap via three key techniques: source-code instrumentation, RTL-simulation trace collection, and a novel reverse-mapping algorithm that associates low-level timing events in synthesized hardware with high-level control-flow constructs. Crucially, it abandons the “compiler-perfection” assumption, instead exposing how concrete compilation decisions impact end-to-end latency. Evaluated on multiple real-world accelerator designs, Petal identifies subtle, manually elusive bottlenecks—enabling targeted manual optimizations that reduce total execution cycles by up to 46.9% for one application.

This work addresses the challenge of memory inefficiencies—such as redundant allocations and suboptimal usage—in large-scale software systems, which often lead to significant resource waste and performance degradation. Existing optimization approaches lack end-to-end automation and struggle to scale to codebases exceeding hundreds of millions of lines. To overcome this, we propose MOA, a novel framework that integrates multi-agent large language models with performance profiling data. MOA employs three coordinated agents—Analyzer, Checker Generator, and Patcher—to automatically detect memory anti-patterns, synthesize static checkers, and generate state-machine-guided, semantics-preserving patches. Evaluated on OpenHarmony’s C/C++ codebase (>100 million lines), MOA identified 13 memory anti-patterns (9 previously unknown), pinpointed over 10,000 inefficiency instances, and produced 769 patches with a 92.5% expert acceptance rate, reducing heap memory usage by 42.2% and binary size by 10.6% on average.

Irregular memory accesses induced by pointer chasing in object-oriented programs degrade cache performance, and existing hardware prefetchers struggle to mitigate this issue effectively. This paper proposes a compile-time static analysis technique that, for the first time, constructs a Markov chain model from static program analysis to accurately predict runtime object access patterns in Java programs—without requiring runtime profiling or historical trace data, thereby enabling low-overhead, high-accuracy modeling. We implement a prototype within the OpenJ9 JVM and OMR compiler framework. Experimental evaluation demonstrates that the model faithfully captures real-world access behavior and effectively supports low-intrusion optimizations: specifically, reordering object copying during garbage collection to improve memory locality, which significantly alleviates load latency. Our approach bridges the gap between static analysis and dynamic memory behavior prediction, offering a principled foundation for compiler-driven memory optimization in managed runtime environments.

This work addresses performance degradation in online data-intensive applications, which often stems from workload fluctuations and resource contention but remains elusive to conventional thread-state analysis due to complex cross-thread dependencies. The authors propose an application-agnostic diagnostic approach that leverages eBPF to collect 16 fine-grained metrics across six kernel subsystems—scheduling, VFS, networking, futex, multiplexed I/O, and block device I/O—and integrates a selective thread-tracing algorithm to precisely trace from entry-point threads to bottlenecked resources. By jointly modeling thread dynamics and resource interaction patterns, the method uniquely captures the propagation pathways of performance degradation. It enables low-overhead diagnosis of CPU, disk, lock, and external service contention across diverse workloads while uncovering internal application bottlenecks.

Cache replacement remains a challenging problem in CPU microarchitecture, often addressed using hand-crafted heuristics, limiting cache performance. Cache data analysis requires parsing millions of trace entries with manual filtering, making the process slow and non-interactive. To address this, we introduce CacheMind, a conversational tool that uses Retrieval-Augmented Generation (RAG) and Large Language Models (LLMs) to enable semantic reasoning over cache traces. Architects can now ask natural language questions like,"Why is the memory access associated with PC X causing more evictions?", and receive trace-grounded, human-readable answers linked to program semantics for the first time. To evaluate CacheMind, we present CacheMindBench, the first verified benchmark suite for LLM-based reasoning for the cache replacement problem. Using the SIEVE retriever, CacheMind achieves 66.67% on 75 unseen trace-grounded questions and 84.80% on 25 unseen policy-specific reasoning tasks; with RANGER, it achieves 89.33% and 64.80% on the same evaluations. Additionally, with RANGER, CacheMind achieves 100% accuracy on 4 out of 6 categories in the trace-grounded tier of CacheMindBench. Compared to LlamaIndex (10% retrieval success), SIEVE achieves 60% and RANGER achieves 90%, demonstrating that existing Retrieval-Augmented Generation (RAGs) are insufficient for precise, trace-grounded microarchitectural reasoning. We provided four concrete actionable insights derived using CacheMind, wherein bypassing use case improved cache hit rate by 7.66% and speedup by 2.04%, software fix use case gives speedup of 76%, and Mockingjay replacement policy use case gives speedup of 0.7%; showing the utility of CacheMind on non-trivial queries that require a natural-language interface.