end-to-end timing analysis

To address the low efficiency and difficulty in root-cause localization during pre-signoff MCMM timing debugging in VLSI design, this paper proposes a multi-LLM collaborative intelligent agent system. Methodologically, it introduces (1) the Timing Debugging Relation Graph (TDRG)—the first domain-specific knowledge graph integrating circuit topology and timing constraints; (2) an Agentic RAG framework unifying graph-based retrieval, executable code reasoning, and hierarchical planning; and (3) an end-to-end pipeline for automated report parsing, root-cause identification, and repair recommendation generation. Evaluated on industrial-scale benchmarks, the system achieves 98% success rate on single-report debugging and 90% on multi-report joint debugging, substantially reducing debug turnaround time. This work represents the first systematic adoption of embodied intelligent agents in VLSI timing verification, establishing a new paradigm for AI-driven signoff automation.

Detecting timing constraint violations in real-time systems faces challenges of high runtime overhead and unreliable prediction under short observation windows. This paper proposes a lightweight hybrid approach that integrates low-overhead, runtime event tracing with semi-Markov chain (SMC) probabilistic modeling. System timestamped events are mapped to state transitions, and task execution time is directly characterized via the “absorption time” of the SMC—thereby reducing reliance on strong distributional assumptions. The method simultaneously captures both typical and extreme temporal behaviors within extremely short observation windows. Experimental evaluation on a real-time Linux platform demonstrates that it achieves high-accuracy worst-case execution time (WCET) estimation with less than 1% CPU overhead. The model exhibits strong interpretability and cross-layer analytical capability, significantly improving both the efficiency and practicality of timing verification.

Traditional static timing analysis (STA) suffers from low computational efficiency and poor utilization of heterogeneous hardware in large-scale industrial designs. To address this, we propose HeteroSTA—the first end-to-end CPU-GPU co-execution STA engine. HeteroSTA natively supports multi-precision delay modeling, full SDC constraint parsing, and multi-clock-domain analysis. It employs GPU-accelerated graph traversal and path-based timing analysis algorithms, enabling fully GPU-accelerated end-to-end STA. A zero-overhead flattened API unifies graph-, path-, and timing-query interfaces, while dual deployment modes—shared library and standalone binary—are provided. Experimental evaluation demonstrates significant speedups over baseline tools in standalone mode, within DREAMPlace 4.0, and in timing-driven routing, achieving performance competitive with industrial-grade STA tools. The source code is publicly released to facilitate both academic research and industrial integration.

Traditional simulation-based dynamic timing analysis struggles to balance accuracy and efficiency, and existing gate delay models lack sufficient expressiveness to enable precise, exhaustive path delay analysis for digital circuits. This work proposes a symbolic execution framework integrated with an analytical gate delay model that automatically generates symbolic delay expressions for all paths under a given input transition ordering. For the first time, it incorporates an analytical delay model accounting for both drafting effects and multi-input switching into symbolic execution. By employing a path-sensitive, goal-directed inference mechanism together with symbolic pruning strategies, the approach significantly enhances the completeness and precision of timing analysis while effectively mitigating the combinatorial explosion problem.

Extracting high-level message flows from complex SoC communication traces is challenging due to message interleaving and causal ambiguity, which often lead to combinatorial explosion of candidates and misinterpretation of system behavior. This work proposes an architecture-guided, two-stage hierarchical mining approach: it first extracts elementary communication patterns locally at each interface, then globally synthesizes cross-component high-level message flows by leveraging the SoC’s design architecture. By integrating local pattern discovery with global architectural constraints, the method effectively mitigates pattern explosion and ambiguity, substantially improving the accuracy of communication behavior modeling. Experimental results on both synthetic traces and realistic SoC traces generated by GEM5 demonstrate that the proposed technique significantly outperforms existing methods in message flow extraction accuracy, making it well-suited for practical SoC verification scenarios.

Autonomous driving systems currently lack temporal analysis models and implementable software that jointly account for multi-rate asynchronous sensor streams and complex actuation chains, hindering guarantees of end-to-end timing correctness and functional safety. This work proposes, for the first time, a five-dimensional research gap framework—encompassing end-to-end latency, data freshness, temporal skew, probabilistic timing, and fail-safe mechanisms—from a co-design perspective of analytical models and system software. By integrating real-time scheduling theories (e.g., DAG-based and mixed-criticality systems), event- and time-triggered paradigms, ROS 2/Autoware architectures, communication optimizations, and runtime tracing techniques, the study systematically uncovers limitations in current approaches regarding constraint modeling, temporal metrics, resource abstraction, execution variability, and safety integration. The findings lay a theoretical and technical foundation for building a highly reliable temporal assurance framework for autonomous vehicles that is analyzable, observable, and deployable.