circuit-level noise modeling

In the NISQ era, anomalous quantum program behavior arises from the entanglement of software bugs and hardware noise, rendering conventional debugging methods ineffective due to their inability to disentangle these distinct root causes. Method: We propose the first statistically grounded quantum error attribution framework, leveraging probabilistic modeling and hypothesis testing over repeated circuit executions to characterize output distributional properties and construct interpretable, quantitative discriminative metrics that separate software errors from physical noise. Contribution/Results: Evaluated on canonical algorithms—including Grover’s, Deutsch-Jozsa, and Simon’s—the framework achieves significantly higher attribution accuracy than baseline approaches. It transcends the applicability limits of classical debugging paradigms in quantum settings and delivers the first theoretically sound and practically deployable error classification tool for quantum software engineering.

Existing quantum compilers rely on noise models that fail to capture context-dependent anomalous behaviors—such as crosstalk and scheduling errors—leading to significant performance disparities among semantically equivalent circuits on real hardware. This work proposes QRisk, a framework that, for the first time, automatically extracts, validates, and leverages backend-specific anomalous circuit patterns from actual hardware execution data to guide compilation optimizations. QRisk employs delta debugging to isolate compact anomalous fragments, verifies their stability through repeated executions and calibration windows, and disrupts harmful patterns during compilation by commuting gate structures. Experimental results demonstrate that QRisk reduces excess noise by 24% and 45% on IBM’s ibm_fez and ibm_marrakesh backends, respectively, confirming both the backend specificity of anomalous patterns and the efficacy of the proposed optimization strategy.

Conventional homogeneous noise models fail to characterize quantum error correction performance on superconducting quantum processors due to spatially non-uniform qubit noise. Method: We introduce the concept of “Boundaries of Acceptable Defects” (BADs) to quantify how individual qubit physical error rates and their spatial positions affect logical error rates in rotated surface codes. Leveraging the STIM simulation framework, we perform large-scale sampling over distance-3–17 surface code circuits under heterogeneous noise models. Contribution/Results: We find that defective qubits with physical error rates ≤0.75% exert negligible impact on logical fidelity—provided appropriate code distances and qubit layouts are selected. However, spatial non-uniformity in error rates significantly degrades fault-tolerance performance. Crucially, this work reframes qubit defects and system uniformity as a continuous spectrum rather than a binary pass/fail criterion. It establishes a quantitative evaluation framework for fault-tolerant quantum computation on non-ideal hardware and provides concrete hardware fidelity targets for scalable quantum processor design.

Quantum circuit fidelity is severely degraded by hardware noise, topology constraints, and compilation choices; yet the coupled impact of compiler strategies (qubit mapping, routing, optimization level) and hardware parameters (noise spectrum, connectivity, scale) remains poorly quantified. Method: We propose a noise-aware full-stack design space exploration (DSE) framework integrating Qiskit-based compilation modeling, hardware sensitivity analysis, fidelity prediction, and quantum error correction (QEC)-aware simulation. Contribution/Results: Our work is the first to quantitatively demonstrate that judicious selection of initial qubit layout and routing can suppress hardware errors more effectively than conventional error mitigation techniques. We further establish that hardware–software co-design remains critical even in QEC-enabled scenarios. Experiments across diverse noisy intermediate-scale quantum (NISQ) and prospective fault-tolerant architectures show an average 12.7% improvement in expected fidelity, alongside reductions in circuit depth and gate count. The framework delivers actionable mapping strategies and hardware configuration guidelines for both near-term noisy and future fault-tolerant quantum systems.

This work addresses the challenge of error mitigation in distributed quantum computing, where communication-induced noise complicates the application of conventional zero-noise extrapolation (ZNE) techniques. The study presents the first systematic comparison between global and local ZNE strategies, evaluating their performance under heterogeneous local and network noise by partitioning quantum circuits into subcircuits and incorporating teleportation-based noisy communication primitives. Surprisingly, increasing the number of quantum processing units (QPUs) enhances the efficacy of global ZNE, achieving up to a 48% reduction in error in a six-QPU system. These findings uncover a novel trade-off among circuit structure, partitioning strategy, and network noise characteristics, while demonstrating strong scalability for global ZNE in distributed settings.

This work addresses the challenge that quantum hardware noise is device-specific, hindering the cross-device generalization of error mitigation strategies. To overcome this limitation, the authors propose a transfer learning–based approach for cross-device noise modeling and correction: a residual neural network noise model pretrained on a source device is fine-tuned using only a minimal number of samples (K=20) from the target device. Experiments on real IBM quantum hardware demonstrate that, on the ibm_marrakesh device, this method reduces the KL divergence of the output distribution from 1.6706 to 1.1924 with just 20 samples, achieving a 28.6% improvement over zero-shot transfer and closing 34.9% of the performance gap. This result provides the first empirical validation of the feasibility of fine-tuning cross-device noise models under extremely low-sample conditions.

Quantum hardware noise significantly flattens the variational energy landscape of the Quantum Approximate Optimization Algorithm (QAOA) for constrained binary optimization problems, thereby degrading algorithmic performance. This work proposes a device-agnostic metric—Landscape Span Compression (LSC)—to quantify noise-induced landscape distortion. Experiments on IBM’s ibm_fez processor demonstrate that LSC robustly characterizes noise severity compared to four existing metrics and effectively informs parameter transfer and error mitigation strategies. The study reveals that noise compresses the landscape span by 24–30% without shifting the optimal solution; feasible solutions at the optimal parameters remain 1.5–1.7 times more probable than random sampling; calibrated noise models account for only ~42% of the observed performance degradation; and zero-noise extrapolation yields limited gains while substantially increasing uncertainty.

Current quantum hardware exhibits highly spatially non-uniform noise, yet existing circuit cutting methods do not systematically account for such heterogeneous noise profiles, leading to exponentially growing sampling overhead. This work proposes a hardware noise-aware circuit cutting framework that explicitly incorporates spatial noise non-uniformity into the cutting strategy for the first time. By unifying gate and wire cutting within a single modeling framework and leveraging real-device noise maps to optimize subcircuit allocation and execution constraints, the method achieves exponential overhead reduction while maintaining low-noise alignment. Notably, it requires only minor relaxation of device constraints to avoid high-noise regions. Experiments demonstrate an average 5–54× reduction in required circuit executions on 20-qubit circuits and, for the first time, enable feasible cutting of 50-qubit circuits and application-level benchmarks, substantially outperforming conventional strategies.

Current quantum computing platforms are constrained by noise and limited qubit counts, hindering the realization of scalable systems. This work proposes a unified analytical framework that rapidly predicts the logical error rates of leading quantum error-correcting codes across mainstream hardware and distributed architectures by modeling two key factors: code structure and two-qubit gate overhead. For the first time, this framework analytically reproduces the qualitative trends observed in large-scale simulations and precisely identifies the dominant sources of logical errors—such as circuit volume, routing overhead, or asymmetric noise—across diverse platforms. Experimental validation confirms its cross-platform predictive accuracy and delineates the optimal design regime for distributed quantum error correction, offering critical guidance for the development of scalable distributed quantum computing systems.

Existing quantum compiler benchmarks provide only aggregate fidelity metrics, making it difficult to pinpoint the sources of fidelity loss across different stages of the compilation pipeline. This work proposes the HBR decomposition framework, which partitions compilation into three distinct phases: high-level structure decomposition (H), basis gate translation (B), and routing (R), thereby enabling, for the first time, stage-wise fidelity attribution. Leveraging this model, the study evaluates eight quantum algorithms across varying optimization levels on Qiskit, PennyLane, and TKET, using both noise-aware simulations and real-device experiments on IBM Heron and IonQ Forte hardware topologies. The results accurately predict the relative performance ranking of the SDKs, reveal that the dominant performance bottleneck shifts with algorithm class and optimization level, and uncover phase-specific limitations invisible to conventional holistic benchmarks.