fhe circuit optimization

The high runtime overhead of fully homomorphic encryption (FHE) circuits stems from the coupled growth of multiplicative depth (MD) and multiplicative complexity (MC): optimizing either metric in isolation often degrades the other, and existing approaches lack joint optimization targeting overall runtime. Method: This work introduces e-graphs—the first application of this formalism to FHE circuit optimization—and proposes cut tracing, a novel technique that jointly minimizes MD and MC at the logic synthesis level. By integrating Boolean circuit optimization, cut enumeration, and a multi-objective optimization framework, our method achieves end-to-end integration within two state-of-the-art optimization flows. Contribution/Results: Our approach reduces homomorphic evaluation runtime by up to 40% compared to baseline methods, significantly outperforming single-objective optimization strategies while preserving correctness and security guarantees.

In fully homomorphic encryption (FHE), noise accumulation and modular wraparound errors severely compromise computational correctness, yet existing compilers lack static noise and overflow analysis capabilities, hindering formal program verification. Method: This paper introduces ILA, a correctness-oriented intermediate language for FHE, which—uniquely—incorporates a type system into FHE compilation. Grounded in an extensible, general-purpose type theory, ILA statically characterizes ciphertext noise bounds and modular arithmetic safety margins across multiple schemes (BGV, BFV, TFHE). Crucially, ILA enables formal modeling and automated verification of noise growth and overflow behavior without requiring secret keys. Contribution/Results: ILA significantly enhances functional correctness assurance for FHE circuits. Experimental evaluation demonstrates efficient verification of representative homomorphic programs, establishing a reliable, formally provable security foundation for FHE application development.

Verifying large-scale arithmetic circuits for wide-word operations often incurs prohibitive computational costs due to reliance on arbitrary-precision integer arithmetic, which scales poorly with word length. This work proposes a hybrid algebraic verification approach based on polynomial reasoning that integrates both linear and nonlinear rewriting strategies. Crucially, it introduces— for the first time—a parallel multimodal homomorphic image technique that performs algebraic reasoning simultaneously over multiple prime moduli, thereby entirely eliminating the need for large-integer computations. Implemented in the TalisMan2.0 tool, the method demonstrates significant performance advantages over existing verification schemes on multiplier benchmarks, offering both high efficiency and strong scalability.

To address the high online encryption overhead in Fully Homomorphic Encryption (FHE) systems—which critically limits throughput in high-load scenarios such as outsourced databases—this paper proposes a compile-time ciphertext synthesis framework. It shifts ciphertext generation entirely to compilation time via precomputed basis vectors, zero-encryption reuse, and composition of homomorphic addition and scalar multiplication, enabling runtime-zero encryption during data ingestion. We formally define “random-mode homomorphism” for the first time and prove its IND-CPA security via a hybrid game, rigorously characterizing the security boundaries of basis reuse and structured noise injection. The scheme remains compatible with standard FHE APIs while preserving layout semantics for downstream homomorphic operations. Experimental results demonstrate substantial improvements in batch encoding throughput, establishing an efficient, secure, and deployable paradigm for ciphertext injection in high-throughput FHE pipelines.

This work addresses identity testing for arithmetic circuits containing exponential gates (x ↦ eˣ), i.e., deciding whether two such circuits compute the same real-valued function—specifically, functions of the form P(𝐱)/P′(𝐱), where P and P′ are exponential polynomials. Method: We propose the first efficient randomized black-box identity testing algorithm over finite fields for this class. We formally define the black-box model for exponential circuits and, assuming the Generalized Riemann Hypothesis (GRH), achieve perfect completeness and high-probability soundness; the false positive rate is exponentially suppressible. Contribution/Results: Our algorithm is implemented in Mirage—a compiler presented at OSDI ’25—and deployed in neural network optimization. Empirical evaluation demonstrates significant improvements in transformation correctness and compilation speed, with low overhead, strong robustness, and practical effectiveness.

Existing fully homomorphic encryption (FHE) compilers perform optimizations only at the ciphertext level, which is insufficient to eliminate polynomial-level redundant computations across ciphertexts, thereby limiting performance gains. This work proposes Recifhe, a multi-level FHE compiler that introduces, for the first time, polynomial-level optimization. Recifhe transforms conventional programs into FHE-compatible ones while integrating the RNS-CKKS scheme, achieving finer-grained computation reduction through ciphertext management, global program transformation, and cross-ciphertext polynomial redundancy elimination. Compared to approaches restricted to ciphertext-level optimization, Recifhe delivers an average speedup of 1.25×.

This work addresses the challenge of efficiently supporting polynomial multiplication—a core operation in fully homomorphic encryption and post-quantum cryptography—on general-purpose AI accelerators without dedicated hardware. The authors propose MPX, a dual-mode systolic array architecture that, for the first time, reveals an intrinsic alignment between the wavefront dataflow of systolic arrays and the multiply-accumulate pattern of polynomial multiplication. This insight enables direct polynomial multiplication without requiring Number Theoretic Transform (NTT), while sharing the same hardware used for matrix multiplication. The design incurs only 20% area overhead, leaves matrix multiplication power consumption virtually unchanged, and reduces polynomial multiplication latency by more than 1.2× compared to NTT-based approaches.

Existing fully homomorphic encryption (FHE) schemes struggle to efficiently and accurately support mixed arithmetic and comparison operations within a unified framework, often resorting to costly scheme switching or error-prone polynomial approximations. This work proposes a novel space-switching technique that enables seamless integration of these two operation types in FV-like schemes by leveraging plaintext space reduction from ℤ_{p^r} to ℤ_p, modulus lifting, and digit decomposition. For the first time, this approach achieves error-free, low-overhead hybrid computation within a single homomorphic encryption framework. Experimental results on representative database workloads demonstrate a 17× speedup over conventional scheme-switching methods and a 15× improvement compared to direct comparison approaches, substantially enhancing the practicality of privacy-preserving computation.

This work addresses the practical barriers to widespread adoption of fully homomorphic encryption (FHE)—notably its high computational overhead and programming complexity—by presenting an open-source C++ library built upon the TFHE scheme. The library enables developers to efficiently implement privacy-preserving algorithms using an imperative programming paradigm, supporting encrypted integer and fixed-point arithmetic, logical operations, comparisons, conditional execution, and oblivious array access. Its key innovation lies in a novel FHE-friendly optimized ALU architecture that substantially reduces the number of costly bootstrapping operations. Additionally, the framework incorporates a simulation mode for debugging and complexity analysis without requiring actual encryption or decryption. Experimental results demonstrate up to a 3.9× speedup on representative operations, significantly lowering bootstrapping overhead and providing a highly efficient and accessible foundation for FHE-based applications.

In hybrid homomorphic encryption (HHE), multi-length number-theoretic transform (NTT) computations pose a significant performance bottleneck due to their computational intensity and the lack of unified hardware support. This work proposes Hermes, the first unified NTT acceleration architecture tailored for HHE. Hermes integrates a fully pipelined on-chip compute core, spatiotemporal parallelism, a conflict-free on-chip tiling algorithm, and a hybrid dataflow design to substantially enhance computational intensity while reducing bandwidth demands. By further leveraging optimized HBM burst accesses and data reuse strategies, Hermes achieves high throughput across diverse NTT lengths, outperforming state-of-the-art GPU and FPGA accelerators by 13.6× and 1.3×, respectively.