hardware-aware qec co-design

In fault-tolerant quantum computing (FTQC), classical decoders for quantum error correction (QEC) face severe resource demand fluctuations—peak loads can exceed idle-period requirements by several orders of magnitude—rendering static hardware allocation inefficient (causing underutilization or real-time violations). Method: We propose the first workload-aware decoder virtualization framework and latency-aware dynamic scheduling strategy, enabling elastic, on-demand allocation of hardware decoder resources. Our approach integrates fine-grained syndrome processing modeling, reusable customized decoder designs, and cross-logical-qubit task coordination. Contribution/Results: Evaluated at the 100–1,000 logical qubit scale, our method reduces hardware decoder resource requirements by 10× while strictly guaranteeing real-time decoding latency and fault-tolerance reliability. This breakthrough overcomes a critical scalability bottleneck in the classical processing layer of QEC, providing essential infrastructure for practical FTQC deployment.

Current quantum computing platforms are constrained by noise and limited qubit counts, hindering the realization of scalable systems. This work proposes a unified analytical framework that rapidly predicts the logical error rates of leading quantum error-correcting codes across mainstream hardware and distributed architectures by modeling two key factors: code structure and two-qubit gate overhead. For the first time, this framework analytically reproduces the qualitative trends observed in large-scale simulations and precisely identifies the dominant sources of logical errors—such as circuit volume, routing overhead, or asymmetric noise—across diverse platforms. Experimental validation confirms its cross-platform predictive accuracy and delineates the optimal design regime for distributed quantum error correction, offering critical guidance for the development of scalable distributed quantum computing systems.

High resource overhead impedes scalable fault-tolerant quantum computation. Method: This paper proposes an efficient logical error suppression method leveraging sparse error characterization. Its core innovation is Cycle Error Reconstruction, which estimates only the top ~1% dominant Pauli error rates; combined with learnable low-dimensional physical error features, it enables accurate full error distribution reconstruction via heuristic distribution inference and maximum-likelihood decoding—bypassing the conventional requirement of a complete noise model. Contribution/Results: Evaluated across multiple physically realistic noise models, the method achieves up to a 10× improvement in logical error performance over fidelity-based baseline decoders. It significantly reduces the resource overhead of quantum error correction, offering a practical pathway toward scalable fault-tolerant quantum computing.

This work addresses the stringent latency requirements of quantum error correction, which demands real-time decoding within microseconds—a challenge exacerbated by rapidly increasing computational overhead as logical qubit counts scale. To overcome this, the authors propose THQLink, a scalable real-time decoding framework that tightly couples high-performance computing (HPC) resources with quantum control systems via the low-latency TH-Express interconnect network. Integrating matching-based decoding algorithms, a parallel sliding-window strategy, and a CPU cluster, THQLink achieves per-round surface code decoding in just 1 microsecond while supporting multi-hop network expansion. Experimental results demonstrate an average round-trip latency of only 2.944 microseconds, with each additional network hop incurring merely 130 nanoseconds of overhead. The system successfully enables real-time error correction on distance-19 surface codes and is adaptable across diverse quantum hardware platforms and quantum-centric supercomputing environments.

This work addresses the severe classical resource contention in real-time decoding for fault-tolerant quantum computing with general qLDPC codes. We present the first automated, lightweight pre-decoder generation framework capable of supporting arbitrary qLDPC codes, overcoming the prior limitation to surface codes and substantially reducing manual design effort. The framework integrates an automated pre-decoding algorithm, an optimized ordered statistics decoding (OSD) procedure, and an efficient pipelined hardware architecture, enabling deployment on FPGAs or cryogenic ASICs. Experimental results demonstrate that the pre-decoder autonomously handles over 90% of decoding tasks, reducing the main decoder’s workload by up to 3,963× and cutting OSD computational cost by 72.71%. A single FPGA can support approximately 1,200 logical qubits for BB codes, while the cryogenic ASIC implementation scales to 36,000–360,000 logical qubits within a 1.5 W power budget.

This work addresses the latency and throughput bottlenecks in real-time quantum error correction decoding during the transition from NISQ to fault-tolerant quantum computing. It proposes an adaptive confidence-gated two-stage decoding framework, wherein a lightweight feedforward neural network rapidly processes high-confidence syndromes, while only 3.3%–6.2% of low-confidence samples are refined using minimum-weight perfect matching (MWPM). This approach introduces confidence gating for the first time in rotated surface code decoding, achieving a logical accuracy improvement from 99.21% to 99.81% across code distances d = 3–11, while delivering a high throughput of 4.6×10⁵ samples per second on CPU. The study further establishes a hardware-aware co-design paradigm that jointly optimizes decoding accuracy, computational efficiency, and deployability.

Fault-tolerant quantum computing demands decoders that balance high logical accuracy with ultra-low latency—a trade-off existing approaches struggle to achieve. This work proposes a co-designed algorithm-hardware quantum error correction decoding scheme that introduces, for the first time, a coset ensemble decoding mechanism. It integrates coset-consistent candidate generation, ensemble forest exploration, reverse-order elimination, and lossless graph compression to enhance decoding accuracy while reducing algorithmic complexity. Concurrently, a time-multiplexed hardware architecture is developed, featuring multi-bank memory hashing and hierarchical ID mapping to prevent linear resource scaling with code distance. Evaluated under a circuit-level depolarizing noise model, the proposed approach significantly improves the accuracy-latency trade-off compared to MWPM and Union-Find decoders, achieving up to an 8.2× reduction in FPGA LUT resource consumption.