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Designs and implements low-latency control systems, firmware, drivers, and signal-path logic to achieve microsecond-scale transmission timing and rapid tuning of radio hardware such as SDRs and RF frontends. Work includes bypassing high-level APIs to perform direct low-level SDR tuning, real-time scheduling and interrupt/DMA optimization, minimizing RF frontend switching latency, and analyzing timing budgets to rapidly retune center frequency and bandwidth.
As 6G evolves, Ultra-Reliable Low-Latency Communication (URLLC) must simultaneously achieve 1-ms end-to-end latency and 99.999% reliability—a fundamental trade-off that existing 5G solutions fail to resolve. Method: This paper adopts a hierarchical perspective—spanning physical-layer coding/retransmission, MAC-layer resource scheduling, and cross-layer joint optimization—to systematically analyze the evolution of 5G URLLC techniques, identify performance bottlenecks in vertical applications, and prospectively examine key challenges for low-latency–high-reliability co-design in 6G scenarios. It proposes a cross-layer design framework grounded in joint latency–reliability modeling. Contribution/Results: The work clarifies intrinsic limitations of current approaches under stringent URLLC requirements and explicitly maps adaptation pathways for emerging 6G enablers—including integrated sensing, communication and computation (ISCC), semantic communication, and intelligent reflecting surfaces (IRS)—into the URLLC architecture. It thus provides both theoretical foundations and a concrete technology roadmap for next-generation URLLC systems.
本文开发了软件驱动程序,通过低成本的HackRF One SDR实现精确时间应用,使用AI辅助开发流程,提高了软件维护性并大幅减少了开发工作量。
This work addresses the high latency inherent in wireless multihop networks caused by store-and-forward mechanisms and interference avoidance. To overcome these limitations, the authors propose RF-Zero-Wire, a novel protocol that introduces symbol-level concurrent relaying, enabling nodes to forward frame data symbol-by-symbol without requiring strict time synchronization—thereby bypassing traditional hop-by-hop transmission constraints. By modeling the beat-frequency effect induced by carrier frequency offsets and integrating forward error correction coding, the protocol significantly enhances transmission reliability. Experimental results demonstrate that RF-Zero-Wire achieves end-to-end latency below 1 ms for a 5-hop transmission of a 4-byte frame, with only a 0.16% latency increase per hop for a 16-byte frame—substantially outperforming conventional protocols, which typically exhibit over 100% latency growth per hop.
In software-defined vehicles, mixed-criticality communication faces severe timing isolation challenges due to interference, unpredictable latency, and jitter—especially from concurrent access to the Linux network stack. Method: This paper proposes a full-stack isolation architecture spanning middleware, the network protocol stack, and hardware. It integrates the Data Distribution Service (DDS) framework, fixed-priority non-preemptive scheduling, eXpress Data Path (XDP) bypassing the kernel stack, and dedicated NIC queues to enforce strict temporal isolation between high- and low-criticality traffic. Contribution/Results: The key innovation is an end-to-end deterministic transmission channel that avoids kernel protocol stack contention. Experiments demonstrate that, under intense best-effort traffic interference, real-time traffic maintains sub-millisecond bounded latency and ultra-low jitter—significantly enhancing execution predictability on centralized in-vehicle Linux platforms.
To address the stringent requirements of 5G and beyond—namely per-flow bandwidth guarantees, microsecond-scale end-to-end latency, and dynamic QoS provisioning—this work tackles the fundamental limitation of traditional fixed-function networks, which struggle to support diverse 3GPP QoS configurations in cloud-native architectures. We propose the first fully programmable data plane model for transport networks that comprehensively supports all 3GPP-defined QoS resource types. Implemented in P4 on Intel Tofino switches, our design enables flow-level fine-grained classification, per-flow rate limiting, strict priority scheduling, and latency-aware queue management. Experimental evaluation demonstrates sub-1 ms end-to-end latency for critical flows, near-zero packet loss, and robust QoS stability under congestion. The solution significantly enhances service assurance capabilities for ultra-reliable low-latency applications.
This work presents a fully connected four-node wireless mesh network based on the Zynq UltraScale+ RFSoC platform to support multi-stream, real-time, uncompressed 4K video transmission. By designing a custom physical and MAC layer within a shared 200 MHz bandwidth, the system achieves, for the first time, a low-latency, digitally controlled frequency-division duplexing 2×2 MIMO link with runtime dynamic reconfiguration capability. The implementation concurrently operates twelve 99.84 Mbps links, delivering an aggregate throughput of 1.2 Gbps—sufficient to transmit multiple synchronized 4K video streams. Furthermore, the platform provides real-time visualization and monitoring of key performance metrics, including error vector magnitude (EVM), signal-to-interference-plus-noise ratio (SINR), and bit error rate (BER).
This study addresses the high latency and difficulty of adapting large language models (LLMs) to bounded decision spaces in wireless control. To overcome these limitations, this work proposes a lightweight alternative architecture based on System-One reasoning. By leveraging Jev for probabilistic distribution learning, the proposed framework directly models decision distributions over bounded control spaces, elucidating the inherent trade-off between decision quality and inference latency. Experimental evaluations on radio access network (RAN) slicing tasks demonstrate that the proposed method reduces latency by 3.5× while preserving utility, significantly outperforming both LLM-based and conventional baselines. These results validate its potential as an effective low-latency decision-making interface for wireless networks.
本文提出Deterministic-5G框架,通过统一的无线资源分配策略解决工业闭环控制中5G通信确定性不足的问题,提高了控制周期完成的可预测性和可靠性。
This work addresses the diverse performance and resource-efficiency requirements of emerging applications for network switches by proposing SPAC, a co-designed framework for automated FPGA-based switch generation that integrates protocol and architecture. SPAC leverages a domain-specific language, a modular high-level synthesis (HLS) component library, trajectory-aware design space exploration, and multi-fidelity simulation to enable joint protocol–microarchitecture optimization and efficient customization. Experimental results demonstrate that, compared to fixed-architecture approaches, SPAC reduces LUT usage by up to 55% and BRAM consumption by up to 53% across various workloads, while achieving latency improvements of 7.8%–38.4%, maintaining low packet loss rates, and incurring only modest resource overhead.
研究通过结合概率设计时延分析与Kuksa实现监控,解决了软件定义车辆中因中间件通信导致的时间不确定性问题。
This study addresses the lack of empirical evaluation of NVIDIA ConnectX NICs’ high-precision scheduling and hardware timestamping capabilities under real-world conditions, which has hindered clear assessment of their suitability for stringent timing requirements in deterministic networks such as 5G fronthaul and Time-Sensitive Networking (TSN). Leveraging an FPGA-based nanosecond-precision measurement platform, this work presents the first public quantification of the hardware timestamp accuracy and Accurate Scheduling transmission timing performance of the ConnectX-7 NIC. Experimental results show that cross-device timestamp deviations are approximately ±7–8 ns, and 99% of scheduled frames are transmitted within ±900 ns of their target time, with rare outliers reaching up to 5 μs. These findings indicate that the NIC meets the tens-of-microseconds timing demands of 5G fronthaul but falls short of the sub-microsecond precision required by TSN, thereby filling a critical gap in industrial empirical understanding of this hardware’s deterministic networking capabilities.