cross-platform compilation

This work addresses the challenge of constructing reproducible software stacks in high-performance computing (HPC) and AI convergence scenarios, where constraints such as lack of root privileges, network isolation, and heterogeneous language environments hinder conventional tooling. For the first time, it systematically applies Nix’s fully isolated build model together with its declarative flake configuration system to HPC-AI hybrid environments, enabling unified management of C/C++ and Python dependencies. By automatically generating Apptainer containers, the approach ensures consistency between local development and deployment on supercomputing systems. The method effectively resolves critical issues including dependency discovery, system library leakage, and cross-project composition, achieving highly reproducible deployments across non-root workstations and production clusters. It demonstrates clear advantages over traditional module systems, Conda environments, and manual containerization, while also highlighting current gaps in Nixpkgs’ coverage of machine learning packages.

To address the lack of systematic continuous verification and secure release mechanisms in open-source hardware design, this paper pioneers the systematic adaptation of software CI/CD paradigms to the hardware domain, proposing a general-purpose framework for automatic hardware specification mining and continuous deployment. Methodologically, it integrates HDL static analysis, machine learning–driven specification inference, formal verification, and cloud-native automated pipelines, implemented in the prototype system Myrtha. Key contributions include: (1) the first CI/CD architecture supporting continuous hardware specification generation, verification, and release; (2) a scalable, automated specification mining mechanism that overcomes traditional manual modeling bottlenecks; and (3) substantial improvements in quality assurance, experimental reproducibility, and cross-team collaboration efficiency for open-source hardware development.

ASIC development faces challenges in IP reuse and lacks integrated hardware-software co-verification and unified build infrastructure. Method: This paper introduces SoCMake—the first unified SoC build system supporting cross-compilation of Chisel/SystemRDL hardware descriptions with C/C++/assembly code. It integrates RTL generation, simulation, firmware compilation, and SoC configuration into a single workflow, overcoming the limited software compilation support of conventional hardware build tools. By deeply embedding SystemC, the RISC-V toolchain, and CMake’s extensibility framework, SoCMake enables automated, abstraction-level–aware co-building across hardware description → RTL → firmware. Contribution/Results: SoCMake has successfully accelerated iterative deployment of radiation-tolerant RISC-V SoCs in high-energy physics applications. After open-sourcing, it has become a de facto standard for generic SoC generation, reducing overall SoC development time by over 40% in empirical evaluations.

This work addresses the challenge of automatically repairing software build failures during cross-Instruction-Set-Architecture (ISA) migration. To this end, we introduce Build-bench—the first end-to-end evaluation benchmark specifically designed for this scenario. Build-bench innovatively integrates architecture-aware reasoning, tool-augmented inference, and executable validation, enabling multi-turn autonomous repair via structure extraction, content modification, build execution, and log-driven feedback. We systematically evaluate six state-of-the-art large language models (LLMs) on 268 real-world build-failing packages; the best-performing model achieves a 63% build repair success rate. Our analysis reveals, for the first time, substantial disparities among models in tool-calling strategies and iterative repair behaviors. This work establishes a reproducible, executable evaluation paradigm and provides empirical foundations for LLM-driven cross-architecture software migration.

This paper addresses engineering challenges in migrating large-scale cloud warehouse workloads from x86 to Arm instruction set architectures (ISAs), proposing a source-code recompilation–centric paradigm—distinct from binary translation. Drawing on nearly 40,000 real-world code commits at Google, we establish the first systematic task taxonomy for large-scale ISA migration. Our approach integrates static analysis, automated code refactoring, machine learning–assisted modifications, and CI pipeline monitoring to drive open-source ecosystem–based, full-stack software reconstruction. The methodology has been deployed internally at Google to automate x86-to-Arm migration across production systems, significantly improving efficiency while surfacing critical legacy bottlenecks. Key contributions include: (1) formalizing a recompilation-first framework for ISA migration; (2) introducing a principled, empirically grounded task classification system; and (3) empirically validating AI’s pivotal role in migration automation—providing an industry-reusable blueprint and opening new research directions in ISA migration for academia.

This work addresses the frequent failures in continuous integration (CI) builds of embedded open-source software, which often stem from cross-compilation complexities, board-specific configurations, and toolchain constraints. These failures are compounded by heterogeneous, ephemeral build logs that are difficult to reuse. To tackle this challenge, the authors propose PhantomRun, a framework that enables standardized reproduction of historical failed builds through a build log abstraction layer, metadata standardization, containerized replay environments, and heterogeneous log parsing techniques. PhantomRun is the first system to support large-scale, controllable replay of failed embedded CI builds, offering a unified, machine-readable interface for build artifacts and metadata. Evaluated on 4,628 failed runs, PhantomRun successfully reconstructed 91.8% of the builds, with 98% preserving the original execution outcomes, demonstrating high reproducibility fidelity.

This work proposes PhantomRun, a novel framework that leverages large language models (LLMs) to automatically repair compilation failures in continuous integration (CI) pipelines for embedded open-source software—a domain often plagued by hardware dependencies, syntax errors, and build script issues that incur substantial debugging overhead. PhantomRun integrates build logs, source code, historical fixes, and error diagnostics to generate and validate repair patches. The framework incorporates an adapter layer to ensure compatibility with diverse CI platforms such as GitHub Actions and GitLab CI, as well as multiple build systems. Experimental evaluation on four widely used embedded software projects demonstrates that PhantomRun successfully resolves 45% of CI compilation failures, thereby establishing the effectiveness and practicality of LLMs in this challenging context.

This work addresses the persistent challenge of inconsistent development and execution environments faced by researchers operating across heterogeneous computing platforms—ranging from laptops and workstations to supercomputers and cloud infrastructures. To overcome this, the authors propose a modular and portable software ecosystem featuring a unified command-line interface that enables seamless orchestration and execution of scientific workflows. The system ensures cross-platform consistency, reproducibility, and scalability, thereby streamlining computational research across diverse hardware configurations. Its practical efficacy has been demonstrated through successful integration into the plan4res project under the European Union’s Horizon 2020 initiative, where it effectively supported complex, large-scale scientific workflows in varied computing environments.

A “dual-language gap” persists between algorithm development in high-level languages and hardware implementation in low-level HDLs. Method: This paper introduces the first MLIR-based high-level synthesis (HLS) toolchain natively supporting Julia—compiling Julia kernels directly to vendor-agnostic, synthesizable SystemVerilog RTL without language extensions or manual annotations, while natively integrating AXI4-Stream protocol support. It innovatively enables hybrid static-dynamic scheduling to balance expressiveness and controllability. Contribution/Results: The generated RTL operates stably at 100 MHz on FPGA. On signal processing and mathematical benchmarks, throughput reaches 59.71%–82.6% of leading C/C++ HLS tools. This significantly improves end-to-end development efficiency and hardware portability—from algorithm specification to synthesized RTL—while preserving Julia’s composability and productivity.

This work addresses the challenges in edge and embedded application development—namely, heterogeneous software stacks, multi-language runtimes, and difficult debugging—which lead to rigid deployment workflows and complex fault diagnosis. To overcome these limitations, the paper proposes a novel architecture enabling unified end-edge-cloud development. Its core components include a single programming language, a retargetable runtime system, a local recording and replay mechanism for distributed events, and a cross-platform deployment framework. This design breaks down traditional debugging barriers in edge–cloud collaborative development, facilitating seamless scalability, consistent testing, and flexible deployment across heterogeneous environments. Evaluation of the prototype system demonstrates that the proposed approach significantly simplifies deployment procedures and enhances fault diagnosis efficiency.