embedded systems programming

Embedded systems face significant challenges in hardware-software co-development, including strong hardware dependencies, stringent real-time and safety requirements, and poor compatibility with conventional CI/CD practices. Method: Through a systematic literature review of 20 academic and industrial studies, we establish the first DevOps practice taxonomy specifically for embedded systems; propose a hardware-aware CI/CD framework supporting closed-loop hardware testing, resource-constrained execution, and safety compliance; and identify and address critical gaps in deployment automation and observability. Contribution/Results: We synthesize toolchain design, automated testing strategies, pipeline lightweighting, and firmware security practices into a structured knowledge framework. This work provides both a theoretical foundation and concrete research directions for academia, and delivers a reusable, industry-applicable methodology for realizing Embedded DevOps.

Addressing stringent energy efficiency, latency, and memory constraints for machine learning inference on battery-powered edge devices, this work proposes a hardware acceleration framework leveraging an embedded Neural Processing Unit (NPU). We employ the ARM Cortex-M55 + Ethos-U55 heterogeneous architecture and introduce a novel GPIO-triggered high-precision power measurement methodology to isolate and quantify the net energy consumption of NPU inference by accurately subtracting idle power. Compared to CPU-only execution, NPU acceleration achieves 7×–125× latency reduction and up to 143× lower net energy per inference. Moreover, we demonstrate, for the first time on microcontrollers, successful deployment of complex quantized models such as SSD-MobileNet. Our core contributions are: (1) establishing a rigorous, reproducible benchmarking methodology for embedded NPU energy efficiency; and (2) empirically validating simultaneous breakthroughs in functional scalability—supporting larger models—and superior energy efficiency.

This study addresses the persistent gap between theoretical control performance and its practical realization in real-world robotic systems, often caused by inadequate discretization, insufficient real-time guarantees, and weak error handling in control software. For the first time from a software engineering perspective, the authors systematically analyze 184 open-source robotic controllers through code review, empirical analysis, and test evaluation, uncovering common deficiencies in application scenarios, implementation details, and verification practices. The findings reveal that most implementations fail to properly account for critical system constraints, and their testing strategies inadequately validate the theoretical assurances they claim. This work highlights a significant disconnect between implementation quality and theoretical promises, offering concrete directions and practical guidelines for developing reliable, verifiable robotic control software.

This work addresses the challenge of deploying real-time, low-power multi-object tracking on edge devices, where conventional Kalman filters struggle to efficiently leverage general-purpose neural processing units (NPUs). For the first time, the authors present an end-to-end deployment of both linear and extended Kalman filters (LKF/EKF) on a commercial low-power NPU without requiring custom hardware. They introduce three algebraic graph rewriting techniques—precomputation of negative projection matrices, fusion of static-shape tensors, and block-diagonal batch parallelization—to ensure all computations execute entirely within the NPU’s matrix engine. Evaluated on an Intel Core Ultra Series 2 platform, the optimized batch EKF achieves 223.35 FPS at 13.43 W, while LKF reaches 408.73 FPS at 14.05 W, reducing dynamic energy consumption by up to 97.9% compared to CPU-based implementations.

This work addresses the challenge of deploying real-time, high-precision control for nonlinear robotic systems—such as drones—in battery-powered scenarios, where existing GPU-based solutions are hindered by excessive power consumption and computational overhead. To overcome this limitation, the paper presents the first hardware acceleration architecture specifically designed for Model Predictive Path Integral (MPPI) control, implemented on an FPGA. By leveraging a customized parallel design, the proposed accelerator significantly improves the energy efficiency of the MPPI algorithm. Simulation results demonstrate that the architecture not only generates more accurate trajectories but also achieves substantial reductions in energy consumption, offering an efficient and deployable control solution for autonomous robotic systems.

Real-time Model Predictive Control (MPC) for resource-constrained microcontrollers—e.g., ARM Cortex-M7—is severely limited by memory footprint and computational latency, hindering deployment on ultra-lightweight robotic platforms. Method: We propose a structured Alternating Direction Method of Multipliers (ADMM) solver tailored for embedded MPC, leveraging problem decomposition, hand-optimized embedded C code, and fixed-point arithmetic to minimize both memory usage and execution time. Contribution/Results: Our solver achieves nearly 10× speedup over the state-of-the-art OSQP solver and, for the first time, enables MPC closed-loop control at >500 Hz on a 27-g quadrotor. It supports high-bandwidth trajectory tracking and dynamic obstacle avoidance. Crucially, we tightly integrate ADMM with the inherent structural properties of MPC—such as block-banded sparsity and separable constraints—yielding the first lightweight, real-time MPC framework deployable on microcontrollers. This work provides a practical, optimal-control-based solution for autonomous navigation in miniature robotics.

This study addresses the severe timing unpredictability arising from shared resource contention in multicore SoCs when integrating high-level autonomy with low-level flight control on general-purpose operating systems for modern drones. For the first time, it quantitatively evaluates the impact of the PREEMPT_RT Linux kernel on worst-case latency of a 250 Hz flight control task on the Raspberry Pi 5 platform, comparing scheduling performance between SoftIRQ deferred execution and real-time direct-wakeup pathways. Through kernel activation path analysis, system stress testing, and temporal determinism assessment, the work demonstrates that the standard Linux kernel exhibits worst-case latencies exceeding 9 ms, whereas PREEMPT_RT reduces this by 88% to below 225 µs. The study further identifies hardware memory contention as the primary source of residual jitter, significantly enhancing the temporal reliability of flight control tasks.

This work addresses the limitations of existing approaches for deploying neural networks on low-power microcontrollers, which rely on static proxy metrics like FLOPs or oversimplified assumptions that fail to capture real-world energy consumption, memory usage, and scheduling constraints, often leading to suboptimal model selection. To overcome this, the authors propose CREST, a novel framework that introduces hardware-in-the-loop evaluation into neural architecture search for microcontroller units (MCUs). CREST enables joint optimization of model architecture, target hardware platform, scheduling policy, and deployment configuration through a configurable workflow. It supports quantization-aware search, cross-platform backends, reproducible search trajectories, and scoring based on actual measured energy and scheduling behavior. Evaluated on an inertial odometry task, CREST reduces real-world energy consumption by over 40% compared to models selected via conventional proxy metrics, while also revealing significant shifts in the Pareto frontier under continuous inference with duty-cycled scheduling and highlighting cross-board deployment overheads.

This work addresses the challenge of enabling multi-megawatt AI/HPC facilities to respond to grid dispatch signals within seconds while precisely regulating GPU power consumption. The authors propose a three-layer predictive control architecture that coordinates regulation across millisecond, second, and hour timescales, augmented by a deterministic safe-island bypass mechanism to achieve rapid closed-loop response from grid commands to GPU power. The study innovatively demonstrates on real hardware that AI supercomputers can serve as flexible grid loads and introduces a real-time PUE correction mechanism to ensure that scheduling commitments are honored at the metering level. Experimental results on a three-GPU V100 platform show an end-to-end response latency of 97.2 ms—6.9× faster than Nordic fast frequency reserve requirements—and reduce cooling-related efficiency penalties by 2.5–5.8 percentage points across six national grid replay scenarios.

This work addresses the challenge of achieving bounded, verifiable, and deterministic coordination in safety-critical real-time autonomous systems operating under uncertainty. It proposes a hardware-enforced semantic coordination architecture that, for the first time, directly maps a topic-based communication space Petri net (TB-CSPN) coordination mechanism onto the FPGA hardware layer. By leveraging hardware primitives to construct a native semantic coordination layer, the approach ensures deterministic execution of time synchronization, semantic gating, authorization constraints, and bounded coordination behaviors—without relying on software mediation. The design decouples low-level interaction management from high-level semantic reasoning, thereby preserving software adaptability while guaranteeing hardware-level reliability. This integration yields a highly dependable real-time system architecture with formally verifiable safety assurances, deterministic coordination, and bounded latency.

This work addresses the significant accuracy degradation often observed in hardware-aware neural architecture search when deploying low-precision models on edge devices, primarily caused by numerical discrepancies between training and inference. To mitigate this issue, the authors propose integrating FP16 low-precision training directly into the search pipeline, imposing FP16 numerical constraints during both architecture fine-tuning and evaluation stages to jointly optimize structural efficiency and numerical robustness. Notably, this approach achieves end-to-end alignment with the numerical characteristics of the target hardware—Intel Movidius Myriad X VPU—without altering the search space or evolutionary strategy. Evaluated on an on-orbit ship segmentation task, the method attains an mIoU of 0.826 on a model with 95,791 parameters, recovering approximately two-thirds of the accuracy drop incurred by post-training quantization, which reduces mIoU from 0.85 to 0.78.