fixed-point arithmetic

Addressing the challenge of simultaneously achieving accuracy, performance, and energy efficiency in scientific computing—particularly under compute-intensive and memory-bandwidth-limited regimes—this paper proposes a cross-domain computational paradigm for mixed-precision algorithm design. The approach integrates domain expertise to rigorously define accuracy boundaries with first-principles numerical methods and AI-accelerated hardware (e.g., low-precision tensor cores). It systematically combines error modeling, mixed-precision algorithm restructuring, software-stack adaptation, and hardware-software co-optimization. Empirical evaluation on representative scientific simulations demonstrates up to 8× speedup in solution time and substantial energy reduction. Crucially, the method delivers robust acceleration not only for compute-bound workloads but also for memory-bandwidth-limited applications—achieving moderate yet consistent gains. This work establishes a generalizable methodology and practical implementation framework for efficiently leveraging AI-accelerator hardware in high-performance scientific computing.

Approximate computing faces fundamental challenges in jointly optimizing accuracy, energy efficiency, and performance for compute-intensive applications such as AI and digital signal processing (DSP). Method: This work proposes, for the first time, a unified classification framework and quantitative evaluation methodology integrating application-specific and microarchitectural-level approximation techniques. It establishes a full-stack approximation technology taxonomy—spanning algorithms, instruction sets, ALUs, compute-in-memory units, and configurable-precision accelerators—alongside an application-mapping model. Contribution/Results: Through systematic benchmarking of over 120 approximation techniques across 15 representative workloads—including image processing, speech recognition, and neural network inference—the study rigorously characterizes their applicability boundaries and achievable gains. The findings provide both theoretical foundations and practical guidelines for principled approximation selection and hardware-software co-design, enabling informed trade-offs in real-world deployment.

To address the high computational cost and low hardware efficiency of floating-point operations in deep learning training, this paper proposes a hardware-aware low-precision logarithmic fixed-point training method tailored for accelerators. The approach innovatively incorporates a bit-width–aware mechanism into logarithmic addition approximation, jointly optimizing piecewise linear approximation and simulated annealing to achieve Pareto-optimal trade-offs between accuracy and hardware overhead. Leveraging the logarithmic number system (LNS) and bit-accurate C++ simulation, end-to-end training is realized using 12-bit integer arithmetic. Experimental results on VGG-11 and VGG-16 demonstrate accuracy comparable to 32-bit floating-point training, while reducing multiply-accumulate (MAC) unit area by 32.5% and energy consumption by 53.5%. This work establishes a novel hardware–software co-design paradigm for low-precision deep learning training.

This work addresses the challenge of balancing dynamic range and precision in numerical representation for memory-constrained embedded and edge AI systems. The authors propose WINT, a weighted integer format that enables flexible trade-offs between precision and range through configurable allocation of mantissa and exponent bits at design time. They derive an analytical model for average relative error and introduce, for the first time, a floating-point-like representation supporting user-defined bit widths. Efficient error evaluation is achieved via O(1)-complexity approximations based on harmonic series and Taylor expansions. Experiments demonstrate that with word lengths of 12 bits or more, WINT using just 2 exponent bits reduces average relative error by 12–33% compared to integer baselines while doubling the dynamic range; with 3 exponent bits, it further extends the range by up to 16× and lowers error by 15–50%.

This work addresses the reliance of stochastic rounding (SR) on high-entropy random bits in low-precision (e.g., FP16) and mixed-precision computing, revealing a previously overlooked systematic bias induced by finite-bit random sources (FBSRs)—a bias invisible under infinite-precision theory yet detrimental to numerical reliability. Through rigorous error modeling, floating-point rounding analysis, and empirical training (e.g., ResNet-18), we quantitatively characterize the bias magnitude across multiple FBSR schemes for the first time, demonstrating up to a 1.2% degradation in training accuracy. Our study extends the reliability assessment framework for low-precision computation by explicitly incorporating FBSR-induced bias as a critical dimension. We further propose a low-bit SR implementation framework that explicitly controls bias while preserving efficiency, and release open-source, reproducible code. This work bridges theoretical SR analysis and practical low-precision system design, enabling more robust and predictable stochastic quantization in deep learning accelerators.

In statistical computing, extremely small probabilities frequently cause numerical underflow; while traditional logarithmic-space arithmetic mitigates this issue, it incurs substantial precision loss, increased resource consumption, and degraded performance. This paper presents the first systematic analysis of the precision cost inherent in logarithmic representations for statistical computation and proposes replacing them with the novel posit floating-point format to jointly optimize accuracy, efficiency, and hardware resource utilization. We implement and evaluate posit-based accelerators on an FPGA platform, benchmarking basic arithmetic operations and representative bioinformatics statistical workloads against binary64 and logarithmic representations. Experimental results demonstrate that the posit accelerator achieves up to two orders-of-magnitude higher accuracy than the logarithmic accelerator, reduces logic resource usage by 60%, improves execution speed by 1.3×, and doubles throughput per unit hardware resource.

This work addresses the lack of formal verification foundations for the IEEE P3109 low-precision floating-point standard, whose flexible format and novel features—such as stochastic rounding and saturating arithmetic—pose unique challenges. We present the first complete, parameterized formal model of P3109 in the Lean theorem prover, enabling machine-checkable analysis of its semantics, operations, and key algorithms. Our contributions include the first mechanically verified specification of P3109, a proof that FastTwoSum precisely captures overflow error under saturating arithmetic, and the discovery that ExtractScalar fails at 1-bit precision. The accompanying open-source formal library provides a reusable foundation for the reliable verification of low-precision numerical software.

This work proposes a hardware-friendly, multi-width static partitioning floating-point format design based on the golden ratio φ, which automatically allocates exponent and mantissa bit widths for any total bit width N ≥ 4 via a single closed-form rule, achieving a balanced trade-off among precision, implementation efficiency, and mathematical consistency. The key innovations include the first application of the golden ratio to floating-point format design for closed-form determination of exponent width, the introduction of an exact integer identity path derived from Lucas sequences, and the construction of a falsifiable conjecture verification framework. The implementation features an RTL generator spanning GF4 to GF256, a high-precision integer accumulator, and an FPGA codec; on a Xilinx Artix-7 device, GF16 achieves 323 MHz and passes all 35 verification tests. The proposed rule accurately reproduces the exponent widths of nine existing formats and consistently extends them up to GF1024.

This work addresses the absence of an efficient, consistent, and parameterizable standard for low-bit-width floating-point representations and arithmetic in modern machine learning. The authors propose a family of configurable binary floating-point formats that flexibly support customizable bit-width, precision, signedness, and infinity handling, with a unified operational semantics grounded in the closed extended real number system. By introducing a kappa-approximation metric to characterize implementation error and integrating parameterized formats with stochastic rounding, saturation modes, and exception-free arithmetic, they construct a formally verified floating-point arithmetic framework. This design substantially enhances hardware throughput while preserving predictable and verifiable numerical behavior.

This work addresses the accuracy degradation of nonlinear activation functions in hardware implementations caused by quantization and truncation. To tackle this issue, the authors propose the Full-space Quantization-driven Architecture (FQA), which, for the first time, comprehensively models the coefficient space affected by quantization. By decoupling the bit-widths across different computational stages and integrating a target-guided binary-window (TBW) acceleration algorithm, FQA efficiently searches for optimal piecewise polynomial approximation coefficients. The architecture supports flexible and configurable hardware mapping. When applied to the Sigmoid function, FQA reduces area and power consumption by over 50% compared to the state-of-the-art, significantly decreases the number of segments, and achieves the best-reported maximum absolute error (MAE) performance.

This work addresses the lack of synthesizable and formally verified IEEE-754 floating-point support in hardware description languages generated by current large models. It presents the first unified framework that simultaneously produces synthesizable SystemVerilog RTL, an SMT-LIB formal model, and a Lean 4 proof artifact from a single source, ensuring semantic consistency among all three through structural binding and machine-checked equivalence, thereby preventing semantic drift. Leveraging a bit-vector intermediate representation, the approach combines Yosys-to-SMT miter verification, SMT floating-point theories, and correctly rounded specifications over dyadic domains to formally verify 24 floating-point operators: non-multiplicative operators are exhaustively proven equivalent to SMT theory, while FP32 multiplication and fused multiply-add (FMA) are formally shown to be correctly rounded in Lean. An optimized 98-bit FMA pipeline achieves 268 MHz in Nangate45 and is proven bit-accurate against an exact reference model in Lean.

This work addresses the high latency, power consumption, and area overhead of conventional division hardware, particularly the lack of efficient approximate implementations in the posit number system. The authors propose a low-precision approximate multiply-divide unit tailored for posits, which uniquely integrates reciprocal approximation directly into the posit decoder. By exploiting the mathematical symmetry inherent in the posit representation, the design rapidly generates reciprocal approximations using a small lookup table (LUT) and a single subtraction operation, while unifying support for both multiplication and division. Implemented in TSMC 90 nm CMOS technology, the proposed unit achieves a 78.8% reduction in power-delay product and occupies only 46.33% of the area compared to an exact division implementation, simultaneously enhancing overall multiplication efficiency within posit-based systems.