fpga implementation

To address low LUT mapping accuracy and insufficient delay–area optimization in FPGA logic synthesis, this paper proposes FuseMap: a novel framework that jointly models ASIC standard-cell mapping and FPGA LUT mapping for the first time, enabling an incremental co-optimization architecture. It incorporates reinforcement learning to dynamically select logic units and determine mapping strategies, achieving design-specific optimization. FuseMap further supports joint tuning across multiple technology libraries and mainstream mapping tools. Experimental evaluation on ISCAS, ITC, VTR, and EPFL benchmark circuits demonstrates that, compared to state-of-the-art methods, FuseMap reduces critical-path delay by 12.3% on average, decreases logic area by 9.7%, and improves mapping accuracy—evidenced by an 8.5% increase in LUT coverage—thereby significantly enhancing overall FPGA synthesis quality.

This work addresses the performance bottleneck in deep learning accelerators on FPGAs caused by data transfers between Block RAMs (BRAMs) and Digital Signal Processing units (DSPs), which rely heavily on global routing resources, leading to increased wirelength, congestion, and critical-path delay. To mitigate this issue, the authors propose a lightweight architectural enhancement that introduces dedicated direct interconnects between BRAMs and DSPs without altering the overall FPGA architecture or compromising compatibility with existing CAD tools. A complementary placement algorithm is developed to identify and optimize BRAM-DSP macro blocks, substantially reducing reliance on global interconnects. Evaluated on an Agilex-10–like FPGA fabric, the approach achieves up to a 25% improvement in maximum operating frequency (Fmax) and a 49% reduction in wirelength for deep learning layers, while imposing no adverse effects on non-deep-learning benchmarks.

Existing LLM-based HDL generation benchmarks evaluate only functional correctness, neglecting critical FPGA constraints—particularly hardware resource efficiency (e.g., LUT utilization)—and suffer from narrow scenario coverage, limiting their ability to distinguish models’ resource optimization capabilities. Method: We propose the first resource-efficiency–oriented benchmark for LLM-generated HDL: it encompasses 56 real-world FPGA designs across 12 application categories; introduces LUT, FF, and BRAM utilization as primary evaluation metrics; and establishes a scalable, resource-aware evaluation framework integrating Xilinx Vivado synthesis and implementation flows with automated comparative pipelines. Results: Experiments reveal substantial variation in LUT usage among state-of-the-art LLMs—up to 3.2×—demonstrating the benchmark’s strong discriminative power and practical utility for assessing and advancing resource-aware HDL generation.

To address the area-efficiency bottleneck in FPGA logic blocks—where LUTs and carry-chain adders cannot operate concurrently due to shared input routing resources—this paper proposes the Double Duty architecture. It repurposes four existing input wires to bypass the LUT and directly drive the carry chain, enabling, for the first time, concurrent LUT and adder utilization within a single logic block without increasing input pin count. We implement circuit-level and CAD-level models within an open-source FPGA toolchain targeting a Stratix-10-like architecture, and evaluate the design using Kratos, Koios, and VTR benchmark suites. Results show an average 13.0% reduction in logic area (−21.6% on Kratos, −9.3% on Koios, −8.2% on VTR), a 9.7% average improvement in area-delay product, and no degradation in critical-path delay.

This work addresses the inefficiency of traditional FPGA design flows, which neglect switching activity data from behavioral simulation and thus struggle to guide power optimization effectively. Existing approaches often rely on fixed thresholds or limited design awareness, incurring significant area overhead. To overcome these limitations, we propose Simopt-Power, a context-aware framework that integrates simulation-derived activity metadata with lightweight structural features—such as timing proximity, logic depth, and fanout—to accurately identify high-impact regions. Rather than using empirical tuning, our method incorporates architecture-aware parameters, including LUT size and mapping constraints, and jointly optimizes area-delay product (ADP) and power-delay product (PDP). Implemented within the open-source Yosys/ABC flow, Simopt-Power achieves an average 6.8% reduction in dynamic power on the Koios deep learning accelerator benchmark while limiting LUT area overhead to within 11.2%.

This work addresses a critical gap in existing AIG-based technology mapping methods, which neglect the distribution of complementary edges (inverters), leading to a discrepancy in delay estimation between technology-independent optimization and technology-dependent mapping—particularly detrimental to critical paths. To bridge this gap, the authors propose a delay-driven preprocessing technique that leverages self-dual and self-anti-dual Boolean function transformations to redistribute complementary edges prior to mapping, thereby optimizing inverter placement along critical paths. This approach represents the first application of such Boolean transformations to complementary edge redistribution, effectively reconciling the modeling disparity of inverters in the synthesis flow. Evaluated on the EPFL combinational benchmark suite, the method achieves an average delay reduction of 0.49%, with up to 3.86% improvement on the sqrt circuit, all while preserving the original logic functionality and timing characteristics.

This work addresses the limitation of traditional FPGA mapping, which performs dual-output packing only after single-output LUT mapping, thereby overlooking pairing optimization opportunities during cut selection. The authors propose an iterative, dual-output-aware LUT mapping framework that, for the first time, feeds dual-output pairing information forward into the cut selection phase and integrates it into Berkeley ABC. The method alternates between cut selection and constrained dual-output matching by generating candidate pairs via sparse support indexing, scoring matches heuristically, adjusting cut costs with compatibility awareness, and validating architectural legality and timing based on physical input unions. Evaluated on EPFL benchmarks, the approach reduces LUT area by 34.96% on average compared to the original ABC, achieves a 15.8× speedup over the previous best method, and further lowers circuit depth by approximately 5% while reducing area by an additional 1%.

This work addresses the challenge faced by domain engineers lacking FPGA expertise in directly translating natural language into deployable hardware. It proposes leveraging large language models (LLMs) to compile natural language specifications into silicon-oriented hardware intermediate representations (IRs), enabling zero-knowledge hardware programming. The study identifies a “representation bottleneck,” demonstrating that IR choice exerts a far greater impact on end-to-end success rates than the selection of LLM. Evaluations on the Lattice iCE40UP5K platform across six IRs—Verilog, VHDL, Chisel, Bluespec, PyMTL3, and HLS C—combined with LLM-based auto-repair reveal simulation pass rates ranging from 3% to 88%, with performance variation across LLMs for the same IR remaining below 1.25×. Notably, LLM-generated designs achieve an 86.5% FPGA synthesis pass rate, substantially outperforming the 68.7% rate of the reference approach.

This work addresses the efficiency and flexibility limitations of general-purpose processor instruction sets when expressing complex or domain-specific computational tasks. The authors propose an FPGA soft-core architecture supporting runtime instruction reconfiguration, which embeds a reconfigurable region capable of dynamically loading custom instruction bitstreams from main memory. The key innovation lies in the design of the LUTstruction-based FPGA architecture, enabling low-latency, fine-to-coarse-grained instruction-level reconfiguration. The study fully validates the “FPGA-in-FPGA” instruction implementation paradigm, demonstrating that the proposed architecture achieves flexible instruction set extension and high-frequency execution without incurring significant clock frequency overhead. Experimental results confirm the efficacy of this approach in enhancing both programmability and performance for specialized computing workloads.

This work addresses the high latency and scarce interposer resource consumption caused by super long lines (SLLs) in multi-die FPGAs, which often become critical-path bottlenecks. It presents the first logic resynthesis approach that explicitly leverages die-partitioning information during logic synthesis, proposing an interconnect-aware, LUT-level transformation that simplifies local circuit structures to reduce SLL usage. Integrated into a complete FPGA CAD flow encompassing packing and placement, the method achieves up to 24.8% and 27.38% SLL reduction on EPFL benchmarks for 2-die and 3-die configurations, respectively. On MCNC benchmarks, it yields an average 1.65% SLL reduction without degrading placement quality, and significantly lowers inter-die connectivity in Koios designs, thereby enhancing physical design flexibility.