low-power embedded systems

To address the challenges of low accuracy, high overhead, and slow response in online power estimation under enhanced hardware heterogeneity and increased parallelism for embedded systems, this paper proposes a lightweight system-level power modeling and real-time monitoring method based on Performance Monitoring Counters (PMCs). The method constructs a modular, linear-correlation-driven power model that requires no microarchitectural details and supports flexible, rapid reconfiguration across DVFS states. Integrated with the Linux kernel-level framework Runmeter, it enables low-overhead PMC sampling and runtime power estimation. Experimental results demonstrate an average power estimation error of only 7.5%, energy error of 1.3%, and worst-case kernel monitoring overhead below 0.7%. This enables effective closed-loop task scheduling and workload-aware DVFS control.

To address the widespread lack of hardware-level power measurement capability in IoT embedded devices, this paper proposes a lightweight software-based power estimation algorithm that integrates an external low-cost USB power meter with data-driven modeling. Our method innovatively combines long-term physical calibration, fine-grained runtime resource feature extraction (e.g., CPU/GPU utilization and frequency), and a lightweight regression model to enable real-time, program-level instantaneous power prediction directly on-device. A custom Linux kernel module ensures synchronized USB sampling and feature acquisition. Evaluated on Jetson Nano and Raspberry Pi platforms, the approach achieves an average estimation accuracy of 92%, with minimal deployment overhead and over 90% reduction in total cost compared to hardware-integrated solutions. Crucially, it requires no hardware modification, offering a high-accuracy, low-cost, and easily deployable power profiling paradigm for resource-constrained IoT devices.

This study challenges the conventional assumption that device power consumption is predominantly determined by hardware, instead investigating the influence of user behavior on system-level energy usage. Leveraging Intel telemetry data, the research employs exploratory data analysis and linear regression models to compare power consumption patterns across users in different countries, with a focus on the United States and China. The findings reveal a statistically significant association between user behavior and overall power draw, demonstrating that behavioral factors exert a non-negligible impact on energy consumption. This insight offers a novel perspective for green computing initiatives and provides empirical evidence to inform stakeholders such as Intel in refining energy-efficiency strategies and mitigating environmental impact.

This work addresses the challenge of high static current in photovoltaic-powered smart sensing networks under low-light conditions, which stems from conventional software-based dynamic power management. To overcome this limitation, the authors propose a hardware-centric, multi-level dynamic power management architecture that completely powers down the microcontroller and non-essential peripherals. Autonomous wake-up is achieved through coordinated operation of an ultra-low-power PMIC, a real-time clock (RTC), and a custom latching circuit. By eliminating software-induced sleep modes and relying entirely on hardware coordination, the system reduces static current to 452 nA, substantially improving energy efficiency and significantly extending the autonomous operational lifetime of sensor nodes in dim lighting environments.

This work addresses the lack of cost-effective, high-precision power measurement solutions for embedded systems, given the high expense and inflexibility of industrial semiconductor test equipment. The authors propose and implement a compact, open-source hardware and software-based system-level power profiling platform that integrates a Raspberry Pi controller, a high-accuracy current sensor, and a microcontroller-based device under test (DUT). A lightweight HTTP interface enables automated firmware deployment, synchronized execution, and remote control. By uniquely combining low-cost open-source hardware with an automated testing workflow, the platform achieves high-resolution current acquisition and supports energy-efficiency benchmarking and regression testing across multiple firmware variants. This significantly enhances the scalability, reproducibility, and practicality of power analysis for embedded systems, making it well-suited for research, prototyping, and educational applications.

This work addresses the neglect of energy efficiency in existing code generation models and the impracticality of large-scale, reproducible hardware-based energy feedback. To bridge this gap, the authors propose the first simulation-based framework for energy-efficient code generation, featuring Green Tea—a deterministic architectural simulator enabling 3.5 million energy evaluations of C++ code snippets. They train energy-aware models via supervised fine-tuning followed by closed-loop reinforcement learning with a novel algorithm (GRPO), and introduce the CARET metric to jointly assess functional correctness and energy efficiency. Experiments on 143 held-out problems demonstrate a 12.63% CARET improvement over baselines, with generated code outperforming human expert implementations in energy efficiency by 58.4%. The study also reveals the misleading nature of traditional throughput-oriented metrics like IPC for energy ranking. The open-sourced dataset and infrastructure eliminate approximately 263,000 CPU hours of reproduction costs.

This study addresses the insufficient attention to energy consumption in contemporary software development and the lack of energy-efficiency tools aligned with developers’ practical needs. Through semi-structured interviews and Mayring’s qualitative content analysis, integrated with the Technology Acceptance Model (TAM), the research systematically investigates developers’ awareness of software energy efficiency, the barriers they encounter in practice, and their requirements for AI-assisted tools. From the developer perspective, the study identifies core design principles for effective energy-efficiency tooling: delivering actionable energy-saving recommendations, enabling low-intrusion integration into existing development workflows, and ensuring transparent disclosure of data usage and quantified energy savings. These findings offer a user-centered design pathway for green software engineering, substantially enhancing both the perceived usefulness and adoption likelihood of energy-efficiency tools among developers.

This study addresses the common oversight of full lifecycle carbon emissions in hardware upgrade decisions by proposing a lifecycle-aware simulation framework. The framework uniquely integrates workload characteristics, location-specific time-varying grid carbon intensity, and multiple embodied carbon allocation strategies—such as uniform amortization and front-loading—with multi-generation CPU power models to dynamically evaluate the total carbon footprint of different deployment scenarios. Experimental results demonstrate that, particularly under low-utilization conditions or in regions with cleaner electricity grids, extending the operational lifespan of existing hardware can substantially reduce overall emissions. These findings challenge the prevailing assumption that newer hardware is inherently more environmentally sustainable and offer a novel paradigm for greener computing practices.

This work addresses the high instruction overhead and software complexity inherent in traditional soft processors, which rely on explicit instructions to read sensors and generate PWM signals within control loops. The authors propose an innovative architecture that maps high-frequency peripheral inputs directly to general-purpose registers and fully offloads PWM generation to dedicated hardware, thereby enabling zero-instruction sensor access and continuous actuation without software intervention. Implemented on a 32-bit, five-stage pipelined MIPS-style RISC soft core, the design incorporates direct peripheral-to-register-file write ports, a single-cycle multiplier, and hardware-based PWM logic. Experimental results demonstrate a reduction in the control loop cycle count from 91 to 43, eliminating five critical instructions; under a 20 ms control frame, the system achieves a real-time margin of 7,300–15,000×, substantially simplifying software and enhancing computational efficiency.