process technology evaluation

Poor generalization in wafer defect detection for semiconductor manufacturing—stemming from end-to-end models’ neglect of dynamic inter-stage process dependencies and structural commonalities across products and fabrication processes—is addressed in this work. We propose a manufacturing-stage-decoupled modular temporal neural network. Our architecture decomposes quality prediction into composable, interpretable stage-specific modules that jointly learn from multimodal sensor time-series data, enabling stage-aware feature extraction and cross-process knowledge transfer. Evaluated across diverse wafer types and fabrication processes, our method achieves a 12.7% average improvement in fault detection accuracy over state-of-the-art end-to-end models. Moreover, it supports root-cause attribution for quality deviations, delivering both strong generalization capability and process-level interpretability—key requirements for practical deployment in high-mix, low-volume semiconductor manufacturing environments.

This work addresses the time-consuming nature of parameter extraction and inspection algorithm development caused by complex 3D structures and EUV stochastic defects in advanced semiconductor nodes. We propose a generalizable deep learning framework based on high-speed scanning probe microscopy images. By leveraging machine learning to replace conventional customized image processing algorithms, this framework enables automated feature recognition, critical dimension parameter extraction, and nanoscale defect detection across diverse layers, structures, and devices. The core innovation lies in establishing a unified intelligent analysis paradigm that significantly shortens algorithm development cycles while enhancing inspection accuracy. Consequently, the proposed approach effectively satisfies the stringent requirements of high-throughput in-line process control in semiconductor wafer fabs.

为解决氧化物半导体晶体管TCAD校准耗时且依赖专家的问题，提出了一种基于代理的自动化校准流程，通过测量-TCAD残差和局部灵敏度测试优化模型参数。

Industrial data-driven models for continuous processes often suffer from long-term model-process mismatch due to dynamic process shifts, risking operational instability or equipment damage. To address this, we propose a lightweight, real-time online model validity verification method. Our approach innovatively offloads the validation task to an Intel Tofino-based programmable switch, establishing an In-Network Computing architecture that overcomes latency and bandwidth bottlenecks inherent in conventional cloud- or edge-based validation. By integrating prior process knowledge modeling with real-time variable comparison detection, the method achieves millisecond-level state identification and response. Experimental evaluation on a laboratory-scale water treatment platform demonstrates significant improvements in detection accuracy and real-time performance, validating both feasibility and engineering practicality in realistic industrial settings.

In semiconductor manufacturing, high variability in process routes—caused by rework, stochastic waiting, and other factors—hampers root-cause analysis of wafer defects. To address this challenge, we propose Partial Trajectory Regression (PTR), a novel framework integrating counterfactual reasoning with representation learning. PTR introduces two learnable embeddings: *proc2vec*, encoding individual process steps, and *route2vec*, capturing structural patterns of variable-length, heterogeneous process trajectories. This enables end-to-end regression over irregular trajectory sequences—overcoming the fundamental limitation of conventional fixed-dimensional vector regression methods. Evaluated on real-world production data from the NY CREATES wafer fab, PTR significantly improves accuracy in identifying critical defect-inducing process steps. The framework establishes a new, interpretable, and scalable paradigm for root-cause analysis in complex, dynamic manufacturing systems.

This work addresses the lack of cost-effective, high-precision power measurement solutions for embedded systems, given the high expense and inflexibility of industrial semiconductor test equipment. The authors propose and implement a compact, open-source hardware and software-based system-level power profiling platform that integrates a Raspberry Pi controller, a high-accuracy current sensor, and a microcontroller-based device under test (DUT). A lightweight HTTP interface enables automated firmware deployment, synchronized execution, and remote control. By uniquely combining low-cost open-source hardware with an automated testing workflow, the platform achieves high-resolution current acquisition and supports energy-efficiency benchmarking and regression testing across multiple firmware variants. This significantly enhances the scalability, reproducibility, and practicality of power analysis for embedded systems, making it well-suited for research, prototyping, and educational applications.

This study addresses the quality control challenges in additive manufacturing arising from its layer-by-layer fabrication process and high degree of customization. It presents the first systematic adaptation of the Six Sigma DMAIC methodology tailored to this context. By integrating multi-source sensing and measurement data across the entire manufacturing chain—including materials, design, process parameters, and post-processing—the work employs advanced techniques such as deep learning, machine learning, design of experiments, simulation, ontological analysis, and network science to model the complex relationships among design inputs, process variations, and final part quality. The proposed optimization framework enables real-time anomaly detection and simultaneously optimizes lead time and energy consumption, thereby significantly enhancing the quality stability and process controllability of additive manufacturing systems.

This study addresses the growing challenges traditional failure analysis methods face in the era of advanced packaging technologies—such as chiplets, hybrid bonding, and 3D stacking—by conducting an anonymous global survey of over 100 semiconductor design, packaging, and failure analysis organizations. The findings reveal that 69% of respondents prioritize heterogeneous integration products (mean importance score: 7.92/10), while 54% identify hybrid bonding as the most analytically challenging technique. A strong consensus emerges around the need for standardized data formats, with 83% of participants advocating for unified protocols, and high-resolution non-destructive imaging garners substantial support (mean score: 8.18/10). The research systematically identifies critical pain points in sample preparation and 3D structural inspection, offering empirical insights to guide industry standardization and technological innovation.

This study addresses the dual challenge faced by semiconductor manufacturing: leveraging AI to enhance operational efficiency while complying with emerging sustainability regulations such as the EU’s Carbon Border Adjustment Mechanism (CBAM). Recognizing a structural disconnect between AI-driven process optimization and sustainability governance, the work synthesizes insights from 1,465 scholarly articles to propose a novel six-layer “Safe and Sustainable by Design” (SSbD) architecture grounded in a system-of-systems approach. Integrating virtual metrology, localized federated learning, and defensive regulatory technology, this framework bridges critical knowledge gaps across the entire value chain—from grid to chip—and aligns with global supply chain standards. It transforms regulatory compliance into an innovation catalyst, enabling a traceable, secure, climate-neutral, and circular data value chain for the semiconductor industry.

This work addresses the limited reproducibility and comparability of machine learning research in electronic design automation (EDA), which stems from the absence of open, standardized datasets. To bridge this gap, the authors propose EDA-Schema-V2—the first standardized multimodal data schema encompassing the full EDA flow from logic synthesis to detailed routing. Leveraging open-source PDKs such as SkyWater 130nm and Nangate 45nm, along with the OpenROAD framework, they generate a large-scale open dataset comprising 7,776 design instances, over 275 million logic gates, and 36 million timing paths through systematic sweeps of process corners, clock periods, and placement parameters. The study defines twelve representative prediction tasks and establishes cross-stage predictability baselines, thereby providing a reproducible benchmark for ML-driven EDA research.