hardware-software co-design

Heterogeneous hardware environments exhibit uneven resource distribution, rendering conventional lock mechanisms performance bottlenecks; existing solutions typically target single hardware types and fail to coordinate heterogeneous resources effectively. This paper introduces Modular Lock Decomposition—a novel paradigm that decouples lock functionality into independent, deployable modules (e.g., acquisition, waiting, wakeup) and dynamically assigns each module to appropriate hardware components (e.g., CPU cores, GPUs, FPGAs, cache levels) based on their architectural characteristics, enabling fine-grained, cross-architecture resource adaptation. To our knowledge, this is the first systematic shift in lock design from monolithic structures to hardware-aware modular architectures. Experimental evaluation under typical concurrent workloads demonstrates an average 42% reduction in lock contention latency and a 1.8× throughput improvement, significantly enhancing lock scalability and heterogeneous resource utilization.

To address critical challenges in SoC design—including ambiguous system-level modeling semantics, poor interoperability across heterogeneous computational models (e.g., dataflow and neural networks), and the decoupling of design-space exploration from verification—this paper proposes a co-communication mechanism ensuring semantic consistency across multiple models. The approach establishes an integrated toolchain supporting system-level modeling, simulation-driven verification, hardware-software co-design space exploration, and joint power-performance analysis. Innovatively, it unifies dataflow modeling with system-level abstractions to enable functional correctness verification and quantitative energy-efficiency evaluation for representative applications such as video processing and AI acceleration. Experimental results demonstrate that the methodology significantly improves early-stage SoC design iteration efficiency and enhances the reliability of architectural decision-making.

To address the substantial semantic gap, weak traceability, and difficulty in correctness assurance between specifications and implementations in high-complexity embedded systems design, this paper proposes a component-based design framework grounded in the perfect synchrony hypothesis. Innovatively integrating Quantitative Type Theory (QTT) with language embedding techniques, the framework defines an Embedded-Domain-Specific Language (EDSL) that uniformly supports formal specification, verification, modeling, simulation, and code generation—ensuring end-to-end semantic consistency across the design flow. Evaluated through a case study, the framework enables a fully semantically coherent, end-to-end design process, significantly enhancing correctness guarantees and design transparency. It establishes a novel, formal, and verifiable paradigm for automated embedded systems design.

Software developers face significant challenges integrating custom hardware—such as AI accelerators—into applications, primarily due to high hardware design expertise requirements and a fundamental abstraction mismatch between software and hardware layers. Method: This paper introduces an end-to-end chip auto-generation methodology tailored for software developers. It accepts high-level object-oriented specifications as input and establishes a one-to-one mapping between software objects and physical chip regions to ensure abstraction consistency. We propose the novel “software–chip structural alignment” paradigm, coupled with object-aligned floorplanning, vertically integrated IP modular construction, and formal verification of hardware interactions via a sequence-based type system. Contribution/Results: The approach enables novice developers to produce synthesizable chip designs while guaranteeing semantic consistency between software behavior and hardware implementation, as well as correctness of hardware communication. It substantially lowers the domain-specific knowledge barrier for hardware design without compromising functional fidelity or correctness guarantees.

This work addresses the inefficiencies and semantic inconsistencies arising from separately implementing driver and monitor programs in traditional hardware module testing. To overcome this, the authors propose a domain-specific language (DSL) tailored to hardware communication protocols, which enables the unified specification of both driver and monitor logic through an imperative syntax, thereby ensuring their semantic consistency for the first time. Building upon this DSL, they develop a prototype tool that leverages waveform parsing and transaction-level trace inference techniques to accurately reconstruct protocol-compliant transaction sequences from raw signal waveforms. Experimental results demonstrate that the approach significantly improves development efficiency, with further validation planned on real-world interconnect protocols such as Wishbone and AXI-Stream.

This work addresses the challenge of achieving bounded, verifiable, and deterministic coordination in safety-critical real-time autonomous systems operating under uncertainty. It proposes a hardware-enforced semantic coordination architecture that, for the first time, directly maps a topic-based communication space Petri net (TB-CSPN) coordination mechanism onto the FPGA hardware layer. By leveraging hardware primitives to construct a native semantic coordination layer, the approach ensures deterministic execution of time synchronization, semantic gating, authorization constraints, and bounded coordination behaviors—without relying on software mediation. The design decouples low-level interaction management from high-level semantic reasoning, thereby preserving software adaptability while guaranteeing hardware-level reliability. This integration yields a highly dependable real-time system architecture with formally verifiable safety assurances, deterministic coordination, and bounded latency.

This study addresses the limitations of software-defined vehicles (SDVs) stemming from tight hardware-software coupling, which hinders modularity, interoperability, real-time performance, and over-the-air (OTA) update capabilities. The work presents the first systematic evaluation of hardware abstraction layer (HAL) mechanisms across automotive and non-automotive domains—including smartphones and industrial automation—and establishes a standardized assessment framework tailored to SDV requirements. Comparative analysis reveals that hypervisor-based HALs excel in security, OTA support, and hardware efficiency, whereas middleware-based HALs offer superior portability and modularity. Building on these insights, the paper proposes a hybrid HAL architecture that synergistically combines the strengths of both approaches, delivering a scalable, lifecycle-aware hardware abstraction solution for SDVs that ensures secure isolation while providing standardized interfaces.

To address layout inefficiency, communication redundancy, unmeasurable power consumption, and limited scalability in Multi-Project Wafer (MPW) platforms for large-scale chip education and research, this paper proposes a high-density, low-cost, and scalable on-chip shared architecture. Methodologically: (1) an algorithm-driven automated floorplanning framework maximizes die area utilization; (2) a novel lightweight interconnect and resource-sharing mechanism leverages site-gap regions, eliminating redundant dedicated I/O and memory macros; (3) modular power-domain partitioning and on-die power monitoring enable per-project power characterization. Experimental results demonstrate up to 13× reduction in die area compared to conventional physically co-located MPW implementations, significantly improving resource utilization and project throughput—without requiring expertise in low-power ASIC design.

Hardware disaggregation aims to transcend traditional server boundaries and establish a unified resource pool spanning cabinets or racks, yet faces critical challenges in resource pooling and coordinated scheduling, energy-efficiency optimization, and system-level trade-offs. This paper proposes a cross-layer co-optimization framework integrating system architecture design, resource pooling mechanisms, fine-grained scheduling algorithms, and a multi-objective energy-efficiency evaluation model. It systematically reveals the deep impacts of decoupled architectures on application development, hardware configuration, and power/thermal management. Through numerical modeling and quantitative analysis, we first characterize the three-dimensional trade-off among pooling granularity, scheduling overhead, and energy efficiency—filling a key gap in pooling-scheduling co-optimization research. Experiments demonstrate that our architecture improves resource utilization by 32–47%, reduces Power Usage Effectiveness (PUE) by 0.08–0.15, and significantly enhances adaptability to heterogeneous workloads.

Existing benchmarks struggle to evaluate the end-to-end capabilities of large language models (LLMs) in system-level hardware-software co-design, often assessing hardware and software components in isolation. This work introduces the first benchmark that encompasses the full co-design workflow, requiring an LLM agent to analyze applications, design heterogeneous accelerators, map kernel functions, and deploy a complete system-on-chip (SoC) prototype on an AMD VC707 FPGA. Built upon an open-source SoC platform and a structured repository, the benchmark enables LLMs to jointly reason about and modify both hardware and software stacks. Experimental results show that among five state-of-the-art models, only two successfully generated functional prototypes, achieving a peak speedup of 16.22×, yet with a maximum resource utilization of merely 23.67%, indicating that current LLMs have not yet fully harnessed the potential of hardware acceleration.