closed-loop in-memory computing

This work addresses the challenge of efficiently solving high-precision, large-scale MIMO nonlinear optimization problems using conventional in-memory computing approaches. The authors propose a continuous-time, nonlinear closed-loop in-memory computing architecture that embeds the bounded-constraint zero-forcing decoding problem into a nonlinear feedback dynamical system composed of memristor arrays and current-limiting operational amplifiers, enabling direct solution via physical evolution. This represents the first extension of closed-loop in-memory computing from steady-state linear algebra to continuous-time nonlinear optimization. A mixed-precision iterative refinement method tailored to this system is introduced, supporting high-order modulation schemes such as 256-QAM. Experimental validation on a fabricated chip demonstrates correct dynamic behavior under hardware non-idealities in a 16×16 MIMO system, achieving scalable performance ranging from ultra-low-power approximate to high-accuracy detection.

Conventional design of convex optimization algorithms is often ad hoc and lacks systematic principles. Method: This paper proposes a novel algorithm construction paradigm grounded in RLC circuit modeling: (i) formulate a continuous-time circuit dynamical system whose trajectories converge to the optimizer; (ii) apply automated symbolic discretization coupled with Lyapunov stability analysis to rigorously guarantee global convergence of the resulting discrete-time iterative algorithm. Contribution/Results: This work establishes the first systematic mapping from circuit physics to optimization algorithm design, enabling provably convergent translation from continuous dynamics to discrete algorithms. It uniformly reconstructs classical methods—including gradient descent and Nesterov’s accelerated gradient—and synthesizes multiple new variants, including distributed algorithms. All derived algorithms come with formal convergence proofs, demonstrating the framework’s generality, mathematical rigor, and practical applicability.

This work addresses the lack of efficient and scalable on-chip training capabilities in existing neuromorphic chips, which hinders autonomous adaptive learning. The authors propose a feedback control–based optimizer and demonstrate its first hardware implementation on a real mixed-signal neuromorphic processor, validating its feasibility in physical systems. Through algorithm–hardware co-design and an In-The-Loop training framework, the system enables online learning for single-layer spiking neural networks. Evaluated on binary classification and the nonlinear Yin-Yang task, the approach achieves performance comparable to numerical simulations and gradient-based baselines, thereby demonstrating its effectiveness and practicality for on-device neuromorphic learning.

This work proposes a brain-inspired neural computing framework designed to unify learning, memory, control, and optimization within a single architecture that is scalable, robust, and energy-efficient. By integrating principles from energy landscapes, gradient flows, control theory, and neuroscience, the study introduces a novel paradigm that transcends conventional feedforward networks and backpropagation. Key mechanisms include continuous-time Hopfield networks, dense associative memory, oscillator-based dynamics, and proximal descent dynamics. The resulting architecture achieves markedly improved computational efficiency and biological plausibility, demonstrating superior performance in data-driven control, constrained reconstruction, and large-scale optimization tasks.

This work addresses the urgent need for efficient solutions to differential and matrix equations in artificial intelligence and scientific computing by transcending the energy-efficiency and speed limitations of conventional digital computation. It pioneers a unified framework that integrates both classes of equations within a modern analog computing paradigm. Leveraging hardware platforms such as analog CMOS circuits and memristor crossbar arrays, the study systematically constructs a computational primitive centered on matrix-vector multiplication, thereby uncovering intrinsic connections among differential equation solvers, matrix equation solvers, and in-memory computing. The research highlights the superior energy efficiency and parallelism offered by memristor arrays while rigorously examining critical challenges including numerical precision and scalability, ultimately establishing analog computing as a promising enabler for next-generation high-performance computing.

This work addresses the challenge of deploying AI models on heterogeneous microcontrollers under stringent physical constraints—including memory, power consumption, and thermal limits—while preserving model accuracy, a task where manual tuning proves inefficient. The authors propose the first hardware-in-the-loop co-optimization framework driven by a large language model (LLM) agent, which automatically jointly optimizes both the neural model and firmware through a closed-loop cycle of compilation, flashing, and real-device measurement. Requiring only three iterations for deployment and surpassing human expert performance within seven, the method enables battery-free operation on solar-powered MCUs. Experiments demonstrate 250× compression of vision models (accuracy loss <3.3%) and 400× compression of audio models (feature error rate <6%), achieving efficient deployment in a moose-monitoring camera (96.7% accuracy) and a child speech wearable (8.44% FER).

This work addresses the high sensitivity of measurement-feedback-based Ising machines to hyperparameters under discrete-time operation, which significantly narrows their effective tuning range compared to ideal continuous-time models and limits their optimization performance. The study systematically investigates the discrepancies between discrete-time implementation and continuous dynamics, uncovering the root causes of this hyperparameter sensitivity. Building on this analysis, the authors propose the first targeted mitigation strategy, combining discrete-time modeling, sensitivity analysis, and experimental validation. The proposed approach substantially broadens the effective operating regime, reduces reliance on precise hyperparameter settings, and thereby enhances the robustness, stability, and practical utility of hardware Ising machines for solving combinatorial optimization problems.

Analog and mixed-signal (AMS) integrated circuits (ICs) lie at the core of modern computing and communications systems. However, despite the continued rise in design complexity, advances in AMS automation remain limited. This reflects the central challenge in developing a generalized optimization method applicable across diverse circuit design spaces, many of which are distinct, constrained, and non-differentiable. To address this, our work casts circuit design as a graph generation problem and introduces a novel method of AMS synthesis driven by deep reinforcement learning (AstRL). Based on a policy-gradient approach, AstRL generates circuits directly optimized for user-specified targets within a simulator-embedded environment that provides ground-truth feedback during training. Through behavioral-cloning and discriminator-based similarity rewards, our method demonstrates, for the first time, an expert-aligned paradigm for generalized circuit generation validated in simulation. Importantly, the proposed approach operates at the level of individual transistors, enabling highly expressive, fine-grained topology generation. Strong inductive biases encoded in the action space and environment further drive structurally consistent and valid generation. Experimental results for three realistic design tasks illustrate substantial improvements in conventional design metrics over state-of-the-art baselines, with 100% of generated designs being structurally correct and over 90% demonstrating required functionality.

This work addresses the inefficiency of conventional physical neural networks, which treat nonlinear devices merely as scalar weights and struggle to approximate smooth functions effectively. Inspired by the Kolmogorov–Arnold representation theorem, the authors propose a novel architecture that places trainable nonlinear functions along network connections rather than at nodes, thereby transforming each physical link into a learnable computational unit. This design substantially reduces network size and enhances modeling efficiency for smooth functions, such as those encountered in continuous control tasks, while enabling cross-hardware portability. Implemented using analog bandpass filters based on field-programmable analog arrays, the approach demonstrates architectural generality across both CMOS and memristor platforms. High-accuracy performance is achieved in robotic kinematics, continuous control, and photovoltaic maximum power point tracking with drastically fewer nodes and connections—e.g., only 35,000 connections—than conventional multilayer perceptrons, consuming approximately 30 microwatts when deployed on CMOS hardware.

This work addresses the limited expressivity of modern analog hardware, which is constrained by fixed differential equations and lags far behind software-defined generative models. To bridge this gap, the authors propose the Analog Interaction Systems (AIS) framework, which substantially enhances the representational capacity of analog dynamical systems through time-segmented tunable parameters and latent physical states. By integrating a Wasserstein GAN training strategy, AIS enables end-to-end trainable generative modeling without requiring trajectory alignment. This study presents the first systematic quantification of the expressivity gap between analog systems and neural networks and introduces a hardware-compatible mechanism to close it. On MNIST and Fashion-MNIST, the model achieves FID scores of 27.6 and 80.8, respectively—outperforming prior analog generative models by 3–4×—while consuming only 23 microjoules per image, offering two orders of magnitude energy savings over digital counterparts.