asynchronous i/o

This work addresses the high analytical latency and severe resource contention in HTAP systems caused by traditional ETL pipelines, which entail frequent data movement. To overcome these limitations, the authors propose offloading data transformation logic to an intelligent storage layer that leverages near-data or in-storage computing capabilities to perform format conversion and preprocessing directly at the storage tier. This approach eliminates the overhead of data migration and significantly reduces interference with foreground transactional workloads, thereby enhancing both the performance and real-time responsiveness of analytical queries. Experimental results demonstrate that the proposed architecture achieves a highly reusable, low-latency data processing paradigm under mixed workloads across multiple execution engines, offering an efficient and scalable storage-compute co-design for HTAP systems.

Emerging SSD interface standards exacerbate software incompatibility, suboptimal data placement, system instability, and weak cross-platform support. To address these challenges, this paper proposes Reshim—the first fully userspace shim layer for SSDs. Reshim introduces the novel design paradigm of “isolated data placement logic,” enabling dynamic, interface- and application-agnostic rule deployment via host-device co-designed affinity-awareness and data-lifecycle-driven policies—without modifying the OS or applications. It supports zero-intrusion integration with RocksDB, MongoDB, and CacheLib. Evaluation demonstrates 2–6× higher write throughput, up to 6× lower tail latency, and significant write amplification reduction. Reshim matches ZenFS in overall performance while achieving lower latency, greater placement policy flexibility, and broader generality across storage interfaces and workloads.

This paper identifies a critical gap in high-performance data transfer research: an overemphasis on network bandwidth while neglecting end-to-end bottlenecks—including latency, TCP congestion control, host CPU limitations, and virtualization—leading to severe discrepancies between benchmark results and real-world production performance. To address this, the authors propose a hardware–software co-design paradigm and develop a latency-programmable testbed. Leveraging high-fidelity wide-area network (WAN) modeling and cross-continental 100 Gbps measurements (Switzerland–California), they systematically isolate key constraints at the network edge and host side. Results demonstrate that primary bottlenecks reside predominantly at the network edge—not the core—and that stable, predictable data movement is achieved across 1–100+ Gbps. This significantly enhances performance fidelity in complex, heterogeneous environments.

To address low cross-facility transfer efficiency and high integrity verification overhead for terabyte-scale files in exascale computing environments, this paper proposes a client-driven dynamic chunking mechanism, the first of its kind to be deeply integrated into the Globus platform. Methodologically, it synergistically combines automated chunking scheduling, parallel transfer optimization, and incremental hash-based integrity verification—departing from conventional small-file-centric transfer optimization paradigms. Experimental evaluation demonstrates up to a 3.2× improvement in end-to-end throughput for TB-scale file transfers and an 87% reduction in integrity verification latency compared to baseline approaches. The solution has been deployed and validated across multiple national flagship supercomputing facilities, significantly enhancing performance, reliability, and scalability for large-scale scientific data movement.

To address performance, energy-efficiency, and latency bottlenecks arising from data movement between main memory and processors in data-intensive computing, this paper proposes and systematically advances the practical deployment of Processing-in-Memory (PIM). We introduce a unified PIM architecture framework that innovatively integrates 3D-stacked logic layers, on-die in-memory computing units, memory controller–integrated accelerators, on-chip ECC-enhanced DRAM, and hardware-level RowHammer mitigation. This holistic design significantly reduces data movement overhead, achieving energy-efficiency improvements of several-fold to over an order of magnitude across representative workloads, while ensuring scalability and reliability. The framework establishes a foundation for low-power, high-throughput memory-compute infrastructure applicable to both server and mobile platforms. By bridging architectural innovation with system-level implementation, our work accelerates the transition of PIM from theoretical concept to real-world deployment.

In shared HPC environments, storage resource contention induces I/O congestion, causing performance volatility, task delays, and timeouts. To address this, we propose a control-theoretic, adaptive client-side I/O rate regulation method—the first to embed feedback control into the client scheduling layer of shared storage systems. Our approach relies solely on lightweight, runtime load metrics (e.g., I/O latency, queue length), enabling parameter-free, workload-agnostic congestion control without manual tuning. Evaluation on multi-node clusters demonstrates up to 20% reduction in total execution time, substantial tail-latency improvement, and significantly enhanced system stability and predictability over baseline schedulers. The core contribution is the first closed-loop control framework specifically designed for I/O congestion in shared storage systems—rigorously grounded in control theory yet practical for real-world deployment.

Metadata hotspots constitute a critical bottleneck limiting I/O scalability in HPC and cloud storage systems, often triggered by job launches or checkpoint storms that induce server-level request surges, thereby exacerbating tail latency and degrading throughput. This paper proposes a transparent middleware deployed between clients and metadata servers—requiring no kernel or backend modifications. Its core contributions are threefold: (1) namespace-aware dynamic load balancing, leveraging an enhanced power-of-d sampling strategy; (2) semantics-preserving collaborative caching, enforced via a lease-driven consistency protocol; and (3) an anti-oscillation, self-stabilizing control loop that enables real-time, telemetry-driven adaptation of timeouts and routing policies. Experimental evaluation demonstrates that, compared to round-robin scheduling, the approach reduces average queue length by 23% and mitigates worst-case hotspots by up to 80%, significantly improving both aggregate throughput and tail-latency predictability.

This work addresses the high latency (P95 exceeding 60 seconds) of cross-account, large-scale queries in multi-tenant cloud platforms caused by buffer cache pressure. The authors propose a query-time search space partitioning mechanism that requires no modification to the database physical schema. By dynamically injecting predicates to logically partition data and employing a two-phase heuristic engine to select partition keys and evaluate execution plans—augmented with client-side pagination tokens for stateless horizontal scaling—the approach uniquely integrates cache locality optimization with session-free traversal across partitions. Applicable to any shared-database multi-tenant system, the method reduces P95 latency by 50–97% (reaching 95–97% for high-cardinality queries), increases throughput by 8–10×, and decreases active sessions by 41×. In production, it lowers P95 latency from 61 seconds to 2 seconds across over 14,000 queries.

Datacenter memory tiering is severely constrained by thermal fragmentation: hot and cold objects co-locate within the same physical page, preventing page-granularity reclamation mechanisms from accurately identifying truly hot pages and thus degrading memory efficiency. This paper introduces “address-space engineering”—a novel paradigm that leverages compiler–runtime co-design to dynamically restructure the virtual address space, enabling logical separation of hot and cold objects at the page level. The approach requires no hardware modifications, remains fully compatible with existing memory reclamation backends, and supports automatic object access tracking and transparent migration. Evaluated on ten representative data structures, it reduces memory footprint by up to 70% while incurring only a 3% average runtime overhead. Our method significantly improves the precision and efficiency of hierarchical memory management and represents the first systematic application of virtual address-space remapping to mitigate thermal fragmentation.

This work addresses the challenge of simultaneously achieving high throughput, low latency, and long-context support in large language model (LLM) serving under dynamic traffic and heterogeneous request patterns. Existing systems suffer from inflexibility due to static parallelism strategies. Building upon vLLM, this study presents the first runtime, restart-free switching between data parallelism (DP) and tensor parallelism (TP), dynamically adapting parallel configurations to real-time workload demands through state virtualization. Key enablers include zero-copy weight management, KV cache adaptation, pre-initialized communication pools, and a deadlock-free scheduler, collectively ensuring state consistency and efficient reconfiguration. Experiments across three mainstream models and realistic scenarios demonstrate up to 4.79× and 3.47× performance improvements under high and low loads, respectively, effectively coordinating bursty traffic handling, priority-based scheduling, and long-context inference.