mixed-precision quantization

Whether 16-bit floating-point (FP16) arithmetic alone can robustly support end-to-end neural network training under hardware resource constraints remains a long-standing, systematically unverified question. Method: This paper introduces the first unified framework for classification-tolerant error analysis, integrating theoretical floating-point error modeling with large-scale empirical validation, and implements fully FP16 forward and backward propagation—without any FP32 “master weights” or loss scaling. Contribution/Results: Rigorous evaluation on CIFAR-10, CIFAR-100, and ImageNet demonstrates that pure FP16 training achieves accuracy parity with FP32 or mixed-precision baselines (accuracy deviation ≤ ±0.1%), while accelerating training by 1.8×. All experiments deploy seamlessly on mainstream GPUs with zero code modification. This work bridges a critical gap between theoretical guarantees and practical feasibility of low-precision training.

Existing open-source RTL dot-product units rely on discrete arithmetic units, resulting in low throughput and poor hardware resource utilization. To address this, this paper proposes a configurable, mixed-precision dot-product unit tailored for GPGPU tensor computation. Our approach unifies floating-point and integer arithmetic pipelines, natively supporting multiplication across FP16, BF16, FP8, BF8, INT8, and UINT4 formats, while performing high-precision accumulation in FP32 or INT32. The architecture is extensible to future custom data formats. Implemented as an extension to the RISC-V Vortex GPGPU tensor core and synthesized on an AMD Xilinx Alveo U55C FPGA, the design achieves a 306.6 MHz operating frequency, a 4-cycle latency, and a peak throughput of 9.812 GFLOPS under full pipelining. Experimental results demonstrate substantial improvements in computational efficiency and hardware resource utilization for deep learning workloads.

To address the instability and divergence observed when using the MXFP8 low-precision format in trillion-token LLM pretraining, this work proposes a dynamic scaling factor computation method based on round-to-infinity rounding, integrated with per-block micro-scaling and a customized rounding strategy, enabling stable training on NVIDIA Blackwell architecture. It achieves, for the first time, end-to-end MXFP8 pretraining of an 8B-parameter model on a 15T-token dataset, matching FP16 convergence behavior precisely. The approach reduces GPU memory footprint by ~40% and memory bandwidth requirements by ~35%, without requiring auxiliary precision recovery modules or mixed-precision fallbacks. This yields significantly improved hardware efficiency and scalability for ultra-large-scale training. To our knowledge, it constitutes the first high-fidelity, full-stage viable solution for low-bit LLM pretraining.

To address the high storage costs and stringent lossless fidelity requirements posed by the surge of floating-point data in IoT and high-performance computing, this paper proposes the first GPU-accelerated adaptive lossless floating-point compression framework. Our method introduces three key innovations: (1) a lightweight asynchronous pipelined architecture that implicitly overlaps CPU–GPU data transfers to hide communication overhead; (2) a theoretically guaranteed error-free floating-point-to-integer transformation algorithm; and (3) adaptive sparse bit-plane encoding, robustly handling data sparsity induced by outliers. Evaluated on 12 real-world datasets, our framework achieves an average compression ratio of 0.299—9.1% better than the best prior baseline. Compression and decompression throughput reach 10.82 GB/s and 12.32 GB/s, respectively—both 2.4× higher than the state-of-the-art methods.

High-precision numerical representations of QUBO coefficients severely degrade the efficiency of specialized hardware—particularly quantum annealers—due to excessive bit-width requirements. Method: We propose a branch-and-bound algorithm that uses dynamic range as a precision-complexity metric, the first such formulation to model dynamic range theory explicitly as the optimization objective for QUBO coefficient quantization. Our framework jointly optimizes precision compression and search efficiency while guaranteeing convergence and solution quality. Crucially, it requires no hardware modification—only input coefficient bit-width reduction via preprocessing. Results: Evaluated on real quantum annealing hardware, our method achieves 35–52% average bit-width compression, 1.8× throughput improvement, 2.3× energy-efficiency gain, and maintains optimal solutions with ≥99.2% fidelity.

This work addresses the high latency introduced by traditional decompression in scientific data analysis, which undermines the storage and transmission benefits of compression. To overcome this limitation, the authors propose a multi-stage, error-bounded decompression and homomorphic analysis framework. By abstracting a generic compression pipeline, the framework enables hierarchical partial decompression and introduces homomorphic operation algorithms tailored to three representative scientific analysis tasks, allowing computations to be performed directly on intermediate compressed representations without full decompression. Implemented atop four mainstream compressors and evaluated across five real-world datasets, the approach consistently reduces data access latency and significantly improves analytical efficiency across diverse workloads.

This work addresses the prevalent overuse of double-precision floating-point numbers in numerical programs by proposing an automated mixed-precision tuning methodology. The approach supports user-defined, non-standard low-precision floating-point formats with customizable exponent and mantissa bit-widths, and integrates numerical validation with systematic search within a unified framework to automatically generate program variants that meet prescribed accuracy constraints. Leveraging the PROMISE tool and containerized parallel benchmarking, the method demonstrates that numerous variables across a range of numerical applications and the Rodinia benchmark suite can be safely downgraded in precision. This reduction yields significant improvements in performance while simultaneously decreasing memory consumption and energy usage, all without compromising numerical accuracy.

This work addresses the challenge that traditional FP64 quantum transport simulations cannot leverage the computational advantages of modern GPUs’ low-precision arithmetic, as naive precision reduction often leads to numerical instability. The study systematically analyzes the numerical stability of the Quatrex solver and proposes a precision-aware conversion strategy that balances accuracy and performance. It demonstrates, for the first time, the effective use of low-precision arithmetic in quantum transport simulations that surpass the FP64 exaflop-per-second barrier. By integrating tailored low-precision floating-point formats, stability-preserving mechanisms, and high-performance computing optimizations, the approach achieves a 51% increase in throughput and reduces computational resource consumption by 40% on realistic large-scale benchmarks, all while maintaining solution accuracy.

This work proposes an efficient bfloat16 (BF16)-based emulation approach leveraging Tensor Cores to meet the high-performance demands of single-precision (FP32) matrix multiplication in scientific computing. By integrating FP32 accumulators, dedicated scaling hardware native to the Blackwell architecture, and comprehensive support for subnormal numbers, the method achieves substantial gains in both performance and energy efficiency while preserving high numerical accuracy. We present the first implementation on Blackwell GPUs that simultaneously optimizes accuracy, speed, and energy efficiency for BF16-emulated FP32 general matrix-matrix multiplication (GEMM), outperforming native FP32 SGEMM across all metrics. This advancement establishes a superior low-precision acceleration strategy for scientific applications requiring FP32-level fidelity.

This work addresses the challenge of efficiently executing double-precision (FP64) matrix multiplication (GEMM) on low-precision tensor cores (FP16/FP8/FP4). We propose ADP, an automatic dynamic-precision framework that extends the Ozaki numerical decomposition with unsigned integer slicing, runtime heuristic scheduling, and exception-aware fallback. Crucially, ADP introduces the Exponent Span Capacity (ESC) estimator to enable adaptive precision selection, and performs all computation entirely on-GPU without host intervention. Our key contribution is the first implementation of rigorously FP64-fidelity GEMM on low-precision hardware, supporting seamless degradation to native FP64. Evaluated on the Blackwell architecture, ADP achieves up to 13.2× speedup over cuBLAS FP64 GEMM, with runtime overhead under 10%, significantly improving energy efficiency for high-precision computation.