Bespoke Co-processor for Energy-Efficient Health Monitoring on RISC-V-based Flexible Wearables

2025-11-08

AI Summary

To address the low energy efficiency of machine learning (ML) classification on flexible RISC-V wearable platforms—constrained by limited gate count, large feature size, and high static power consumption—this paper proposes a co-optimized hardware acceleration framework for health monitoring. Our method jointly optimizes coprocessor constants and multi-layer perceptron (MLP) inference mapping via constraint programming, generating a model-specific, area- and power-optimal fixed-coefficient multiply-accumulate (MAC) coprocessor. The coprocessor is integrated with a low-power RISC-V microprocessor fabricated using flexible electronics technology. Experimental results demonstrate that the prototype achieves a 2.35× speedup and a 2.15× improvement in energy efficiency within a 2.42 mm² die area, enabling near-real-time health data analytics and significantly overcoming the energy-efficiency bottleneck of ML inference on flexible platforms.

Technology Category

• Machine Learning: Hardware-aware ML
• Computer Vision: Learning & Optimization for CV
• Humans and AI: Human-in-the-loop Machine Learning

Application Category

• Systems and Infrastructure for Web, Mobile and WoT: Applied ML and AI for Web-based mobile applications
• Security and Privacy: Security and privacy of machine learning and AI applications
• Responsible Web: Machine-in-the-loop, human agency and autonomy

Abstract

Flexible electronics offer unique advantages for conformable, lightweight, and disposable healthcare wearables. However, their limited gate count, large feature sizes, and high static power consumption make on-body machine learning classification highly challenging. While existing bendable RISC-V systems provide compact solutions, they lack the energy efficiency required. We present a mechanically flexible RISC-V that integrates a bespoke multiply-accumulate co-processor with fixed coefficients to maximize energy efficiency and minimize latency. Our approach formulates a constrained programming problem to jointly determine co-processor constants and optimally map Multi-Layer Perceptron (MLP) inference operations, enabling compact, model-specific hardware by leveraging the low fabrication and non-recurring engineering costs of flexible technologies. Post-layout results demonstrate near-real-time performance across several healthcare datasets, with our circuits operating within the power budget of existing flexible batteries and occupying only 2.42 mm^2, offering a promising path toward accessible, sustainable, and conformable healthcare wearables. Our microprocessors achieve an average 2.35x speedup and 2.15x lower energy consumption compared to the state of the art.

Problem

• Developing energy-efficient ML accelerators for flexible health wearables
• Overcoming hardware limitations of bendable RISC-V systems for on-body classification
• Optimizing MLP inference operations within flexible electronics power constraints

Innovation

• Custom co-processor with fixed coefficients for RISC-V
• Constrained programming to optimize MLP inference mapping
• Flexible circuits within power budget of existing batteries