An FPGA-Based Open-Source Hardware-Software Framework for Side-Channel Security Research

2024-07-24

arXiv.org

AI Summary

IoT devices are highly vulnerable to side-channel analysis (SCA) attacks, yet existing SCA research platforms are closed, non-reproducible, and lack integration. Method: This paper introduces the first fully open-source, reproducible, and extensible FPGA-based SCA research framework tailored for IoT scenarios. Built upon a RISC-V SoC, it integrates a custom debug architecture, a dynamic frequency scaling (DFS) actuator, FreeRTOS real-time OS, and a Python-based automation toolchain—unifying attack execution, security evaluation, and rapid deployment of countermeasures. Contribution/Results: The framework uniquely unifies observability, controllability, and protection validation capabilities, significantly lowering the barrier to SCA research. It has been validated on real FPGA hardware with multiple state-of-the-art SCA attacks and mitigation techniques, demonstrating practicality, stability, and strong support for academic research.

Technology Category

• Application Domains: Internet of Things, Sensor Networks & Smart Cities
• Machine Learning: Hardware-aware ML
• Computer Vision: Adversarial Attacks & Robustness

Application Category

• Security and Privacy: Large-scale security measurements
• Systems and Infrastructure for Web, Mobile and WoT: Web performance, measurement, and characterization
• User Modeling, Personalization and Recommendation: Attacks and countermeasures in recommendation systems

Abstract

Attacks based on side-channel analysis (SCA) pose a severe security threat to modern computing platforms, further exacerbated on IoT devices by their pervasiveness and handling of private and critical data. Designing SCA-resistant computing platforms requires a significant additional effort in the early stages of the IoT devices' life cycle, which is severely constrained by strict time-to-market deadlines and tight budgets. This manuscript introduces a hardware-software framework meant for SCA research on FPGA targets. It delivers an IoT-class system-on-chip (SoC) that includes a RISC-V CPU, provides observability and controllability through an ad-hoc debug infrastructure to facilitate SCA attacks and evaluate the platform's security, and streamlines the deployment of SCA countermeasures through dedicated hardware and software features such as a DFS actuator and FreeRTOS support. The open-source release of the framework includes the SoC, the scripts to configure the computing platform, compile a target application, and assess the SCA security, as well as a suite of state-of-the-art attacks and countermeasures. The goal is to foster its adoption and novel developments in the field, empowering designers and researchers to focus on studying SCA countermeasures and Attacks while relying on a sound and stable hardware-software platform as the foundation for their research.

Problem

• Develops FPGA-based framework for side-channel security research.
• Provides IoT-class SoC with RISC-V CPU for SCA analysis.
• Offers open-source tools for SCA attacks and countermeasures evaluation.

Innovation

• FPGA-based SoC with RISC-V CPU
• Debug infrastructure for SCA observability
• Open-source framework for SCA research