Arm DynamIQ Shared Unit and Real-Time: An Empirical Evaluation

2025-03-21

AI Summary

Arm DynamIQ Shared Unit (DSU) lacks empirical validation of real-time isolation guarantees on embedded multicore platforms (e.g., Rockchip RK3568/RK3588, NVIDIA Orin), as its hardware cache partitioning mechanisms are designed for average-case—not worst-case—performance. Method: We develop a DSU support framework spanning OS and hypervisor layers, integrating hardware performance counter monitoring, multi-type interference injection (cache, memory, CPU), and realistic/synthetic workload evaluation to quantitatively assess isolation efficacy against interference characteristics (type, intensity, pattern). Results: DSU achieves practical real-time isolation, but its performance is highly sensitive to interference properties. Based on empirical findings, we derive configuration guidelines and optimization strategies tailored for real-time systems. This work provides the first evidence-based foundation and engineering guidance for trustworthy DSU deployment in safety-critical embedded systems.

Technology Category

• Machine Learning: Hardware-aware ML
• Constraint Satisfaction and Optimization: Distributed CSP/Optimization
• Planning, Routing, and Scheduling: Optimization of Spatio-temporal Systems

Application Category

• Systems and Infrastructure for Web, Mobile and WoT: Web performance, measurement, and characterization
• Security and Privacy: Large-scale security measurements
• Responsible Web: Data and user privacy-enhancing technologies for the Web

Abstract

The increasing complexity of embedded hardware platforms poses significant challenges for real-time workloads. Architectural features such as Intel RDT, Arm QoS, and Arm MPAM are either unavailable on commercial embedded platforms or designed primarily for server environments optimized for average-case performance and might fail to deliver the expected real-time guarantees. Arm DynamIQ Shared Unit (DSU) includes isolation features-among others, hardware per-way cache partitioning-that can improve the real-time guarantees of complex embedded multicore systems and facilitate real-time analysis. However, the DSU also targets average cases, and its real-time capabilities have not yet been evaluated. This paper presents the first comprehensive analysis of three real-world deployments of the Arm DSU on Rockchip RK3568, Rockchip RK3588, and NVIDIA Orin platforms. We integrate support for the DSU at the operating system and hypervisor level and conduct a large-scale evaluation using both synthetic and real-world benchmarks with varying types and intensities of interference. Our results make extensive use of performance counters and indicate that, although effective, the quality of partitioning and isolation provided by the DSU depends on the type and the intensity of the interfering workloads. In addition, we uncover and analyze in detail the correlation between benchmarks and different types and intensities of interference.

Problem

• Evaluating real-time capabilities of Arm DynamIQ Shared Unit
• Assessing cache partitioning for embedded multicore systems
• Analyzing interference impact on DSU isolation performance

Innovation

• Hardware per-way cache partitioning for isolation
• OS and hypervisor integration for DSU support
• Performance counters for interference analysis