🤖 AI Summary
Large language models (LLMs) incur prohibitive computational overhead and poor energy efficiency in hardware design, challenging their practical deployment. Method: This paper challenges the “bigger is better” paradigm by proposing a Small Language Model (SLM) + Agent AI collaborative framework tailored for Verilog design. The framework employs task decomposition, context-aware prompting, multi-turn self-correction, and iterative feedback to enable continual learning and collaborative reasoning with lightweight models. Contribution/Results: Evaluated on the NVIDIA CVDP benchmark, our approach achieves design quality comparable to state-of-the-art LLMs while reducing inference cost substantially. Experimental results demonstrate that integrating lightweight models with structured agent workflows balances performance, energy efficiency, and scalability in complex chip design tasks—paving a novel pathway toward green AI–driven adaptive hardware design.
📝 Abstract
Large Language Model(LLM) inference demands massive compute and energy, making domain-specific tasks expensive and unsustainable. As foundation models keep scaling, we ask: Is bigger always better for hardware design? Our work tests this by evaluating Small Language Models coupled with a curated agentic AI framework on NVIDIA's Comprehensive Verilog Design Problems(CVDP) benchmark. Results show that agentic workflows: through task decomposition, iterative feedback, and correction - not only unlock near-LLM performance at a fraction of the cost but also create learning opportunities for agents, paving the way for efficient, adaptive solutions in complex design tasks.