A 55-nm SRAM Chip Scanning Errors Every 125 ns for Event-Wise Soft Error Measurement

2025-04-11

AI Summary

This work addresses the challenge of distinguishing pseudo-multi-cell upsets (pseudo-MCUs) from distant multi-cell upsets (distant MCUs) in conventional soft-error measurement. We propose an event-level measurement methodology achieving high spatiotemporal resolution. Implemented on a 55-nm SRAM test chip, it integrates a high-speed full-array scan circuit (125 ns/scan), a radiation-hardened PLL, a FIFO-SPI interface, and an on-chip event construction algorithm to enable real-time output of soft-error data with nanosecond-precision timestamps. It achieves, for the first time, sub-nanosecond (<1 ns) inter-device temporal synchronization and micrometer-scale spatial synchronization (tens of micrometers), enabling single-event attribution via correlation with particle detectors. Experimental validation under 80-MeV proton irradiation demonstrates accurate classification of single-bit upsets (SBUs), MCUs, and the two MCU subtypes—overcoming the misclassification limitations inherent in statistical averaging approaches.

Technology Category

• Machine Learning: Hardware-aware ML
• Planning, Routing, and Scheduling: Optimization of Spatio-temporal Systems
• Multiagent Systems: Multiagent Systems under Uncertainty

Application Category

• Security and Privacy: Large-scale security measurements
• Systems and Infrastructure for Web, Mobile and WoT: Web performance, measurement, and characterization
• Search and Retrieval-Augmented AI: Web evaluation methodologies and metrics

Abstract

We developed a 55 nm CMOS SRAM chip that scans all data every 125 ns and outputs timestamped soft error data via an SPI interface through a FIFO. The proposed system, consisting of the developed chip and particle detectors, enables event-wise soft error measurement and precise identification of SBUs and MCUs, thus resolving misclassifications such as Pseudo- and Distant MCUs that conventional methods cannot distinguish. An 80-MeV proton irradiation experiment at RASiS, Tohoku University verified the system operation. Timestamps between the SRAM chip and the particle detectors were successfully synchronized, accounting for PLL disturbances caused by radiation. Event building was achieved by determining a reset offset with sub-ns resolution, and spatial synchronization was maintained within several tens of micrometers.

Problem

• Develops 55nm SRAM chip for real-time soft error detection
• Identifies SBUs and MCUs, resolving misclassifications in conventional methods
• Achieves timestamp and spatial sync for event-wise error measurement

Innovation

• 55-nm SRAM chip scans data every 125 ns
• SPI interface outputs timestamped error data
• Synchronizes timestamps with particle detectors